modify baudrate: 115200

DefaultBuild/multical.clnk

@@ -0,0 +1,49 @@
+-Input=DefaultBuild\cstart.obj
+-Input=DefaultBuild\stkinit.obj
+-Input=DefaultBuild\r_main.obj
+-Input=DefaultBuild\r_systeminit.obj
+-Input=DefaultBuild\r_cg_cgc.obj
+-Input=DefaultBuild\r_cg_cgc_user.obj
+-Input=DefaultBuild\r_cg_serial.obj
+-Input=DefaultBuild\r_cg_serial_user.obj
+-Input=DefaultBuild\r_cg_port.obj
+-Input=DefaultBuild\r_cg_port_user.obj
+-Input=DefaultBuild\owi.obj
+-Input=DefaultBuild\i2c.obj
+-Input=DefaultBuild\uart.obj
+-Input=DefaultBuild\delay.obj
+-Input=DefaultBuild\dipSwitch.obj
+-Input=DefaultBuild\gatectrl.obj
+-Input=DefaultBuild\app_result.obj
+-Input=DefaultBuild\app_cmd_parser.obj
+-Input=DefaultBuild\app_scheduler.obj
+-Input=DefaultBuild\app_owi_service.obj
+-Input=DefaultBuild\r_cg_wdt.obj
+-Input=DefaultBuild\r_cg_wdt_user.obj
+-SECURITY_ID=00000000000000000000
+-DEVICE=C:\Program Files (x86)\Renesas Electronics\CS+\CC\Device\RL78\Devicefile\DR5F10PPJ.DVF
+-DEBug
+-NOCOmpress
+-NOOPtimize
+-OUtput=DefaultBuild\multical.abs
+-OCDBG=84
+-DEBUG_MONITOR=3FE00-3FFFF
+-USER_OPT_BYTE=78FFF8
+-OCDTR
+-LISt=DefaultBuild\multical.map
+-SHow=SYmbol,Total_size
+-AUTO_SECTION_LAYOUT
+-ROm=.data=.dataR
+-ROm=.sdata=.sdataR
+-NOMessage
+-MEMory=High
+-NOLOgo
+-LIBrary=DefaultBuild\multical.lib
+-end
+-Input=DefaultBuild\multical.abs
+-DEVICE=C:\Program Files (x86)\Renesas Electronics\CS+\CC\Device\RL78\Devicefile\DR5F10PPJ.DVF
+-OUtput=DefaultBuild\multical.mot
+-FOrm=Stype
+-NOMessage
+-exit
+

DefaultBuild/multical.map

@@ -0,0 +1,981 @@
+Renesas Optimizing Linker (W3.07.00 )             03-Aug-2026 09:42:27
+
+*** Options ***
+
+-subcommand=DefaultBuild\multical.clnk
+-Input=DefaultBuild\cstart.obj
+-Input=DefaultBuild\stkinit.obj
+-Input=DefaultBuild\r_main.obj
+-Input=DefaultBuild\r_systeminit.obj
+-Input=DefaultBuild\r_cg_cgc.obj
+-Input=DefaultBuild\r_cg_cgc_user.obj
+-Input=DefaultBuild\r_cg_serial.obj
+-Input=DefaultBuild\r_cg_serial_user.obj
+-Input=DefaultBuild\r_cg_port.obj
+-Input=DefaultBuild\r_cg_port_user.obj
+-Input=DefaultBuild\owi.obj
+-Input=DefaultBuild\i2c.obj
+-Input=DefaultBuild\uart.obj
+-Input=DefaultBuild\delay.obj
+-Input=DefaultBuild\dipSwitch.obj
+-Input=DefaultBuild\gatectrl.obj
+-Input=DefaultBuild\app_result.obj
+-Input=DefaultBuild\app_cmd_parser.obj
+-Input=DefaultBuild\app_scheduler.obj
+-Input=DefaultBuild\app_owi_service.obj
+-Input=DefaultBuild\r_cg_wdt.obj
+-Input=DefaultBuild\r_cg_wdt_user.obj
+-SECURITY_ID=00000000000000000000
+-DEVICE=C:\Program Files (x86)\Renesas Electronics\CS+\CC\Device\RL78\Devicefile\DR5F10PPJ.DVF
+-DEBug
+-NOCOmpress
+-NOOPtimize
+-OUtput=DefaultBuild\multical.abs
+-OCDBG=84
+-DEBUG_MONITOR=3FE00-3FFFF
+-USER_OPT_BYTE=78FFF8
+-OCDTR
+-LISt=DefaultBuild\multical.map
+-SHow=SYmbol,Total_size
+-AUTO_SECTION_LAYOUT
+-ROm=.data=.dataR
+-ROm=.sdata=.sdataR
+-NOMessage
+-MEMory=High
+-NOLOgo
+-LIBrary=DefaultBuild\multical.lib
+-end
+
+*** Error information ***
+
+*** Mapping List ***
+
+SECTION                            START      END         SIZE   ALIGN
+.vect
+                                  00000000  0000007f        80   0
+.constf
+                                  00000080  00000093        14   2
+.init_array
+                                  00000094  00000094         0   2
+.sdata
+                                  00000080  00000080         0   2
+.option_byte
+                                  000000c0  000000c3         4   1
+.security_id
+                                  000000c4  000000cd         a   1
+.RLIB
+                                  000000c4  000000c4         0   1
+.monitor1
+                                  000000ce  000000d7         a   1
+.data
+                                  000000d8  0000091a       843   2
+.text
+                                  0000091b  00000acb       1b1   1
+.const
+                                  00003000  0000361d       61e   2
+.textf
+                                  0000361e  000074d7      3eba   1
+.SLIB
+                                  000074d8  00009de0      2909   1
+.monitor2
+                                  0003fe00  0003ffff       200   1
+.bss
+                                  000fb500  000feaed      35ee   2
+.dataR
+                                  000feaee  000ff330       843   2
+.sbss
+                                  000ffe20  000ffe20         0   2
+.sdataR
+                                  000ffe20  000ffe20         0   2
+
+*** Total Section Size ***
+
+RAMDATA SECTION:  00003e31 Byte(s)
+ROMDATA SECTION:  0000110d Byte(s)
+PROGRAM SECTION:  00006974 Byte(s)
+
+*** Symbol List ***
+
+SECTION=
+FILE=                               START        END    SIZE
+  SYMBOL                            ADDR        SIZE    INFO      COUNTS  OPT
+
+SECTION=.vect
+FILE=rlink_generates_04
+                                  00000000  0000007f        80
+
+SECTION=.constf
+FILE=_REL_print
+                                  00000080  00000093        14
+
+SECTION=.option_byte
+FILE=rlink_generates_01
+                                  000000c0  000000c3         4
+
+SECTION=.security_id
+FILE=rlink_generates_03
+                                  000000c4  000000cd         a
+
+SECTION=.monitor1
+FILE=rlink_generates_02
+                                  000000ce  000000d7         a
+
+SECTION=.data
+FILE=DefaultBuild\r_main.obj
+                                  000000d8  000008fb       824
+FILE=DefaultBuild\owi.obj
+                                  000008fc  00000908         d
+FILE=DefaultBuild\i2c.obj
+                                  0000090a  00000911         8
+FILE=DefaultBuild\uart.obj
+                                  00000912  00000917         6
+FILE=DefaultBuild\gatectrl.obj
+                                  00000918  00000918         1
+FILE=DefaultBuild\app_owi_service.obj
+                                  0000091a  0000091a         1
+
+SECTION=.text
+FILE=DefaultBuild\cstart.obj
+                                  0000091b  0000098d        73
+  _start
+                                  0000091b         0   none ,g         * 
+  _exit
+                                  0000098b         0   none ,g         * 
+  _atexit
+                                  0000098d         0   none ,g         * 
+FILE=DefaultBuild\r_cg_serial_user.obj
+                                  0000098e  00000acb       13e
+  _r_uart0_interrupt_receive@1
+                                  0000098e        5f   func ,l         * 
+  _r_uart0_interrupt_send@1
+                                  000009ed        2f   func ,l         * 
+  _r_uart1_interrupt_receive@1
+                                  00000a1c        5f   func ,l         * 
+  _r_uart1_interrupt_send@1
+                                  00000a7b        2f   func ,l         * 
+  _r_iica0_interrupt@1
+                                  00000aaa        22   func ,l         * 
+
+SECTION=.const
+FILE=DefaultBuild\r_main.obj
+                                  00003000  00003438       439
+  _nvm_read_cmd@9@execute_write_coeff_sequence@1
+                                  00003422         3   data ,l         * 
+  _cmd_nvm_read@17@execute_shadow_write_copy_nvm_sequence@1
+                                  00003425         3   data ,l         * 
+  _cmd_15_0000@16@execute_shadow_write_copy_nvm_sequence@1
+                                  00003428         3   data ,l         * 
+  _cmd_crc_42@15@execute_shadow_write_copy_nvm_sequence@1
+                                  0000342b         3   data ,l         * 
+  _cmd_crc_40@14@execute_shadow_write_copy_nvm_sequence@1
+                                  0000342e         3   data ,l         * 
+  _cmd_1a@13@execute_shadow_write_copy_nvm_sequence@1
+                                  00003431         1   data ,l         * 
+  _cmd_14@12@execute_shadow_write_copy_nvm_sequence@1
+                                  00003432         1   data ,l         * 
+  _cmd_15_3c5b@11@execute_shadow_write_copy_nvm_sequence@1
+                                  00003433         3   data ,l         * 
+  _cmd_crc_44@10@execute_shadow_write_copy_nvm_sequence@1
+                                  00003436         3   data ,l         * 
+FILE=DefaultBuild\owi.obj
+                                  0000343a  000034f3        ba
+FILE=DefaultBuild\i2c.obj
+                                  000034f4  000035e1        ee
+FILE=DefaultBuild\gatectrl.obj
+                                  000035e2  0000361d        3c
+
+SECTION=.textf
+FILE=DefaultBuild\stkinit.obj
+                                  0000361e  00003661        44
+  _stkinit
+                                  0000361e         0   none ,g         * 
+  LSTINIT1
+                                  0000362c         0   none ,l         * 
+  LSTINIT2
+                                  00003656         0   none ,l         * 
+  LSTINIT3
+                                  00003661         0   none ,l         * 
+FILE=DefaultBuild\r_main.obj
+                                  00003662  0000569e      203d
+  _RS485_Bridge_Push
+                                  00003662        2b   func ,g         * 
+  _RS485_Bridge_ResetFifo@1
+                                  0000368d         e   func ,l         * 
+  _app_kick_wdt@1
+                                  0000369b         5   func ,l         * 
+  _app_startup_guard_delay@1
+                                  000036a0        27   func ,l         * 
+  _app_clear_uart_runtime_state@1
+                                  000036c7        4d   func ,l         * 
+  _app_runtime_reset@1
+                                  00003714         c   func ,l         * 
+  _rs485_abort_and_reset_pipeline@1
+                                  00003720        29   func ,l         * 
+  _RS485_Bridge_ReadLine@1
+                                  00003749        91   func ,l         * 
+  _Is_V_Response_For@1
+                                  000037da        40   func ,l         * 
+  _UART1_WaitTxIdle@1
+                                  0000381a        2c   func ,l         * 
+  _UART1_SendString_Safe@1
+                                  00003846        39   func ,l         * 
+  _RS485_Bridge_DrainToPC@1
+                                  0000387f        4d   func ,l         * 
+  _hex2byte@1
+                                  000038cc        56   func ,l         * 
+  _is_long_owi_read_len@1
+                                  00003922         8   func ,l         * 
+  _do_stable_owi_read@1
+                                  0000392a        a5   func ,l         * 
+  _parse_x_prefix@1
+                                  000039cf       153   func ,l         * 
+  _OUT_PRINT@1
+                                  00003b22         d   func ,l         * 
+  _send_end_response@1
+                                  00003b2f         7   func ,l         * 
+  _parse_x_v_cmd@1
+                                  00003b36        57   func ,l         * 
+  _send_n_response@1
+                                  00003b8d        2b   func ,l         * 
+  _parse_x_o_cmd@1
+                                  00003bb8        57   func ,l         * 
+  _send_v_response@1
+                                  00003c0f        3f   func ,l         * 
+  _UART0_WaitTxDone_Flag@1
+                                  00003c4e        3f   func ,l         * 
+  _RS485_FlushJunk@1
+                                  00003c8d        1b   func ,l         * 
+  _PC_PrintLine_CRLF@1
+                                  00003ca8        81   func ,l         * 
+  _scan_one_addr_rs485@1
+                                  00003d29       12c   func ,l         * 
+  _build_line_from_rx@1
+                                  00003e55        63   func ,l         * 
+  _detect_protocol@1
+                                  00003eb8        37   func ,l         * 
+  _cmd_unknown@1
+                                  00003eef        10   func ,l         * 
+  _print_owi_write_result@1
+                                  00003eff        5a   func ,l         * 
+  _print_owi_read_result@1
+                                  00003f59        d5   func ,l         * 
+  _run_connect_verify_one_channel@1
+                                  0000402e       1a8   func ,l         * 
+  _print_connect_sweep_result@1
+                                  000041d6        52   func ,l         * 
+  _execute_connect_verify_sequence@1
+                                  00004228        9f   func ,l         * 
+  _execute_direct_read_sequence@1
+                                  000042c7       16f   func ,l         * 
+  _execute_write_coeff_sequence@1
+                                  00004436       1f6   func ,l         * 
+  _execute_shadow_write_copy_nvm_sequence@1
+                                  0000462c       59a   func ,l         * 
+  _execute_basic_owi_job@1
+                                  00004bc6       123   func ,l         * 
+  _execute_owi_service_from_job@1
+                                  00004ce9        44   func ,l         * 
+  _forward_line_rs485_and_bridge@1
+                                  00004d2d       22f   func ,l         * 
+  _process_cmd@1
+                                  00004f5c        6d   func ,l         * 
+  _process_cmd_by_prefix@1
+                                  00004fc9        11   func ,l         * 
+  _process_one_line_now@1
+                                  00004fda       43b   func ,l         * 
+  _process_one_line@1
+                                  00005415        98   func ,l         * 
+  _app_runtime_try_start@1
+                                  000054ad        1a   func ,l         * 
+  _app_job_tick@1
+                                  000054c7        cb   func ,l         * 
+  _handle_uart_command_line
+                                  00005592        9b   func ,g         * 
+  _main
+                                  0000562d        5b   func ,g         * 
+  _R_MAIN_UserInit
+                                  00005688        17   func ,g         * 
+FILE=DefaultBuild\r_systeminit.obj
+                                  0000569f  000056e3        45
+  _R_Systeminit
+                                  0000569f        3e   func ,g         * 
+  _hdwinit
+                                  000056dd         7   func ,g         * 
+FILE=DefaultBuild\r_cg_cgc.obj
+                                  000056e4  0000570d        2a
+  _R_CGC_Create
+                                  000056e4        2a   func ,g         * 
+FILE=DefaultBuild\r_cg_cgc_user.obj
+                                  0000570e  00005710         3
+  _R_CGC_Get_ResetSource
+                                  0000570e         3   func ,g         * 
+FILE=DefaultBuild\r_cg_serial.obj
+                                  00005711  000059f8       2e8
+  _R_SAU0_Create
+                                  00005711        12   func ,g         * 
+  _R_UART0_Create
+                                  00005723        6e   func ,g         * 
+  _R_UART0_Start
+                                  00005791        26   func ,g         * 
+  _R_UART0_Stop
+                                  000057b7        1e   func ,g         * 
+  _R_UART0_Receive
+                                  000057d5        18   func ,g         * 
+  _R_UART0_Send
+                                  000057ed        26   func ,g         * 
+  _R_SAU1_Create
+                                  00005813        12   func ,g         * 
+  _R_UART1_Create
+                                  00005825        6e   func ,g         * 
+  _R_UART1_Start
+                                  00005893        26   func ,g         * 
+  _R_UART1_Stop
+                                  000058b9        1e   func ,g         * 
+  _R_UART1_Receive
+                                  000058d7        18   func ,g         * 
+  _R_UART1_Send
+                                  000058ef        26   func ,g         * 
+  _R_IICA0_Create
+                                  00005915        50   func ,g         * 
+  _R_IICA0_Stop
+                                  00005965         5   func ,g         * 
+  _R_IICA0_StopCondition
+                                  0000596a         5   func ,g         * 
+  _R_IICA0_Master_Send
+                                  0000596f        43   func ,g         * 
+  _R_IICA0_Master_Receive
+                                  000059b2        47   func ,g         * 
+FILE=DefaultBuild\r_cg_serial_user.obj
+                                  000059f9  00005b86       18e
+  _r_uart0_callback_receiveend@1
+                                  000059f9        49   func ,l         * 
+  _r_uart0_callback_softwareoverrun@1
+                                  00005a42         1   func ,l         * 
+  _r_uart0_callback_sendend@1
+                                  00005a43         9   func ,l         * 
+  _r_uart0_callback_error@1
+                                  00005a4c        5c   func ,l         * 
+  _r_uart1_callback_receiveend@1
+                                  00005aa8        31   func ,l         * 
+  _r_uart1_callback_softwareoverrun@1
+                                  00005ad9         1   func ,l         * 
+  _r_uart1_callback_sendend@1
+                                  00005ada         4   func ,l         * 
+  _r_uart1_callback_error@1
+                                  00005ade         1   func ,l         * 
+  _iica0_masterhandler@1
+                                  00005adf        91   func ,l         * 
+  _r_iica0_callback_master_error@1
+                                  00005b70         7   func ,l         * 
+  _r_iica0_callback_master_receiveend@1
+                                  00005b77         8   func ,l         * 
+  _r_iica0_callback_master_sendend@1
+                                  00005b7f         8   func ,l         * 
+FILE=DefaultBuild\r_cg_port.obj
+                                  00005b87  00005bdf        59
+  _R_PORT_Create
+                                  00005b87        59   func ,g         * 
+FILE=DefaultBuild\owi.obj
+                                  00005be0  000063cc       7ed
+  _GPIO_Clear
+                                  00005be0        12   func ,g         * 
+  _GPIO_Input
+                                  00005bf2        11   func ,g         * 
+  _GPIO_Read
+                                  00005c03         9   func ,g         * 
+  _OWI_Release@1
+                                  00005c0c        11   func ,l         * 
+  _GPIO_StrongDriveHighKick@1
+                                  00005c1d        32   func ,l         * 
+  _GPIO_ForceHighKick
+                                  00005c4f         8   func ,g         * 
+  _OWI_DriveLow@1
+                                  00005c57        12   func ,l         * 
+  _OWI_HasTimeout
+                                  00005c69         4   func ,g         * 
+  _OWI_ClearTimeout
+                                  00005c6d         e   func ,g         * 
+  _OWI_GetLastTimeoutByteIndex
+                                  00005c7b         4   func ,g         * 
+  _OWI_GetLastTimeoutBitIndex
+                                  00005c7f         4   func ,g         * 
+  _OWI_Init
+                                  00005c83        1b   func ,g         * 
+  _OWI_Start
+                                  00005c9e        17   func ,g         * 
+  _OWI_Stop
+                                  00005cb5        14   func ,g         * 
+  _OWI_StopRead@1
+                                  00005cc9        17   func ,l         * 
+  _OWI_WaitForFallingEdge@1
+                                  00005ce0        4b   func ,l         * 
+  _OWI_ReadByte_StreamSynced@1
+                                  00005d2b        73   func ,l         * 
+  _OWI_SecureStop
+                                  00005d9e        51   func ,g         * 
+  _OWI_WriteBit
+                                  00005def        37   func ,g         * 
+  _OWI_WriteByte
+                                  00005e26        2a   func ,g         * 
+  _OWI_ReadBit
+                                  00005e50        af   func ,g         * 
+  _OWI_ReadByte
+                                  00005eff        48   func ,g         * 
+  _OWI_T_ReadBytesAndPrint
+                                  00005f47       134   func ,g         * 
+  _owi_result_init@1
+                                  0000607b        21   func ,l         * 
+  _owi_result_latch_timeout@1
+                                  0000609c        29   func ,l         * 
+  _OWI_T_CommandModeRaw
+                                  000060c5        69   func ,g         * 
+  _OWI_CommandModeRaw
+                                  0000612e        69   func ,g         * 
+  _OWI_ReadBytesRaw
+                                  00006197        d3   func ,g         * 
+  _OWI_disable
+                                  0000626a        15   func ,g         * 
+  _OWI_T_CommandMode
+                                  0000627f        26   func ,g         * 
+  _OWI_CommandMode
+                                  000062a5        26   func ,g         * 
+  _OWI_ReadBytesAndPrint
+                                  000062cb       102   func ,g         * 
+FILE=DefaultBuild\i2c.obj
+                                  000063cd  0000654d       181
+  _disable
+                                  000063cd        26   func ,g         * 
+  _I2C_EnablePower
+                                  000063f3         4   func ,g         * 
+  _I2C_DisablePower
+                                  000063f7         3   func ,g         * 
+  _I2C_T_Command_Mode_receiveData
+                                  000063fa        4d   func ,g         * 
+  _I2C_Command_Mode_receiveData
+                                  00006447        3e   func ,g         * 
+  _I2C_Command_Mode_Send
+                                  00006485        c9   func ,g         * 
+FILE=DefaultBuild\uart.obj
+                                  0000654e  00006759       20c
+  _rs485_recover
+                                  0000654e        56   func ,g         * 
+  _UART1_WaitTxIdle@1
+                                  000065a4        2c   func ,l         * 
+  _rs485_set_tx
+                                  000065d0         b   func ,g         * 
+  _rs485_init
+                                  000065db         c   func ,g         * 
+  _UART0_WaitTxDone_Us
+                                  000065e7        2f   func ,g         * 
+  _RS485_Send
+                                  00006616        54   func ,g         * 
+  _RS485_SendString
+                                  0000666a        11   func ,g         * 
+  _uart_send_string
+                                  0000667b        11   func ,g         * 
+  _uart1_send_string
+                                  0000668c        40   func ,g         * 
+  _uart_send_hex
+                                  000066cc        43   func ,g         * 
+  _uart1_send_hex
+                                  0000670f        4b   func ,g         * 
+FILE=DefaultBuild\delay.obj
+                                  0000675a  00006818        bf
+  _delay
+                                  0000675a        18   func ,g         * 
+  _delay_us
+                                  00006772        82   func ,g         * 
+  _delay_ms
+                                  000067f4        25   func ,g         * 
+FILE=DefaultBuild\dipSwitch.obj
+                                  00006819  00006829        11
+  _DipSwitch_Init
+                                  00006819         8   func ,g         * 
+  _DipSwitch_ReadAddr_0to31
+                                  00006821         9   func ,g         * 
+FILE=DefaultBuild\gatectrl.obj
+                                  0000682a  00006bed       3c4
+  _Gate_SetByNum
+                                  0000682a       372   func ,g         * 
+  _Cal_Init
+                                  00006b9c        21   func ,g         * 
+  _Eol_Init
+                                  00006bbd        21   func ,g         * 
+  _GateCtrl_SelectChannel
+                                  00006bde        10   func ,g         * 
+FILE=DefaultBuild\app_result.obj
+                                  00006bee  00006bf7         a
+  _app_result_print_ok
+                                  00006bee         5   func ,g         * 
+  _app_result_print_err
+                                  00006bf3         5   func ,g         * 
+FILE=DefaultBuild\app_cmd_parser.obj
+                                  00006bf8  00007069       472
+  _parse_x_v_addr@1
+                                  00006bf8        62   func ,l         * 
+  _find_payload_pos@1
+                                  00006c5a        1b   func ,l         * 
+  _hex_nibble@1
+                                  00006c75        31   func ,l         * 
+  _hex_pair_to_u8@1
+                                  00006ca6        2f   func ,l         * 
+  _app_cmd_parse_line
+                                  00006cd5       395   func ,g         * 
+FILE=DefaultBuild\app_scheduler.obj
+                                  0000706a  00007105        9c
+  _app_scheduler_init
+                                  0000706a        15   func ,g         * 
+  _app_scheduler_push
+                                  0000707f        38   func ,g         * 
+  _app_scheduler_pop
+                                  000070b7        31   func ,g         * 
+  _app_scheduler_is_empty
+                                  000070e8         9   func ,g         * 
+  _app_scheduler_clear
+                                  000070f1        15   func ,g         * 
+FILE=DefaultBuild\app_owi_service.obj
+                                  00007106  000074cc       3c7
+  _app_owi_from_raw@1
+                                  00007106        86   func ,l         * 
+  _is_long_owi_read@1
+                                  0000718c         9   func ,l         * 
+  _app_owi_read_verified_long@1
+                                  00007195       15e   func ,l         * 
+  _looks_bad_tail@1
+                                  000072f3        5c   func ,l         * 
+  _looks_bad_last_bytes@1
+                                  0000734f        48   func ,l         * 
+  _needs_retry_for_long_read@1
+                                  00007397        3a   func ,l         * 
+  _app_owi_read_basic
+                                  000073d1        a2   func ,g         * 
+  _app_owi_write_basic
+                                  00007473        2d   func ,g         * 
+  _app_owi_write_t_basic
+                                  000074a0        2d   func ,g         * 
+FILE=DefaultBuild\r_cg_wdt.obj
+                                  000074cd  000074d7         b
+  _R_WDT_Create
+                                  000074cd         7   func ,g         * 
+  _R_WDT_Restart
+                                  000074d4         4   func ,g         * 
+
+SECTION=.SLIB
+FILE=isdigit
+                                  000074d8  000074e1         a
+  _isdigit
+                                  000074d8         0   none ,g         * 
+FILE=memcmp
+                                  000074e2  000074f3        12
+  _memcmp
+                                  000074e2         0   none ,g         * 
+FILE=memcpy
+                                  000074f4  00007503        10
+  _memcpy
+                                  000074f4         0   none ,g         * 
+FILE=memset
+                                  00007504  00007511         e
+  _memset
+                                  00007504         0   none ,g         * 
+FILE=sprintf
+                                  00007512  0000760a        f9
+  _sprintf
+                                  00007512        e1   func ,g         * 
+  __REL_sp@1
+                                  000075f3        18   func ,l         * 
+FILE=strchr
+                                  0000760b  00007618         e
+  _strchr
+                                  0000760b         0   none ,g         * 
+FILE=strcpy
+                                  00007619  00007625         d
+  _strcpy
+                                  00007619         0   none ,g         * 
+FILE=strlen
+                                  00007626  00007630         b
+  _strlen
+                                  00007626         0   none ,g         * 
+FILE=strncpy
+                                  00007631  00007644        14
+  _strncpy
+                                  00007631         0   none ,g         * 
+FILE=strstr
+                                  00007645  00007663        1f
+  _strstr
+                                  00007645         0   none ,g         * 
+FILE=toupper
+                                  00007664  00007671         e
+  _toupper
+                                  00007664         0   none ,g         * 
+FILE=_REL_print
+                                  00007672  000095c9      1f58
+  __REL_print
+                                  00007672      1046   func ,g         * 
+  __REL_fltprn@1
+                                  000086b8       941   func ,l         * 
+  __REL_henkan1@1
+                                  00008ff9        28   func ,l         * 
+  __REL_henkan2@1
+                                  00009021        33   func ,l         * 
+  __REL_pri@1
+                                  00009054       298   func ,l         * 
+  __REL_fltgeti@1
+                                  000092ec       19d   func ,l         * 
+  __REL_inmod@1
+                                  00009489       141   func ,l         * 
+FILE=_COM_fdiv
+                                  000095ca  000096f7       12e
+  __COM_fdiv
+                                  00009629         0   none ,g         * 
+FILE=_COM_feq
+                                  000096f8  0000970d        16
+  __COM_feq
+                                  000096f8         0   none ,g         * 
+FILE=_COM_fge
+                                  0000970e  00009723        16
+  __COM_fge
+                                  0000970e         0   none ,g         * 
+FILE=_COM_flt
+                                  00009724  00009739        16
+  __COM_flt
+                                  00009724         0   none ,g         * 
+FILE=_COM_fmul
+                                  0000973a  00009826        ed
+  __COM_fmul
+                                  00009785         0   none ,g         * 
+FILE=_COM_fne
+                                  00009827  00009837        11
+  __COM_fne
+                                  00009827         0   none ,g         * 
+FILE=_COM_ftosl
+                                  00009838  0000983f         8
+  __COM_ftosl
+                                  00009838         0   none ,g         * 
+FILE=_COM_sidiv
+                                  00009840  00009861        22
+  __COM_sidiv
+                                  00009842         0   none ,g         * 
+FILE=_COM_sirem
+                                  00009862  00009881        20
+  __COM_sirem
+                                  00009862         0   none ,g         * 
+FILE=_COM_ulldiv
+                                  00009882  000098ab        2a
+  __COM_ulldiv
+                                  00009882         0   none ,g         * 
+FILE=_COM_ullrem
+                                  000098ac  000098dc        31
+  __COM_ullrem
+                                  000098ac         0   none ,g         * 
+FILE=_REL_f_inf
+                                  000098dd  000098e4         8
+  __REL_f_inf
+                                  000098dd         0   none ,g         * 
+FILE=_REL_f_norm
+                                  000098e5  000098f4        10
+  __REL_f_norm
+                                  000098e5         0   none ,g         * 
+FILE=_REL_f_round
+                                  000098f5  00009907        13
+  __REL_f_round
+                                  000098f5         0   none ,g         * 
+FILE=_REL_fcmp
+                                  00009908  0000993f        38
+  __REL_fcmp
+                                  00009908         0   none ,g         * 
+FILE=_REL_fordered_core
+                                  00009940  0000995b        1c
+  __REL_fordered_core
+                                  00009940         0   none ,g         * 
+FILE=_REL_ftol
+                                  0000995c  00009990        35
+  __REL_ftol
+                                  0000995c         0   none ,g         * 
+FILE=_REL_lldiv
+                                  00009991  00009b96       206
+  __REL_lldiv
+                                  000099ad         0   none ,g         * 
+FILE=_REL_llrem
+                                  00009b97  00009d9a       204
+  __REL_llrem
+                                  00009bb4         0   none ,g         * 
+FILE=_REL_ltosl
+                                  00009d9b  00009dbf        25
+  __REL_ltosl
+                                  00009d9b         0   none ,g         * 
+FILE=_COM_lshr
+                                  00009dc0  00009de0        21
+  __COM_lshr
+                                  00009dca         0   none ,g         * 
+
+SECTION=.monitor2
+FILE=rlink_generates_02
+                                  0003fe00  0003ffff       200
+
+SECTION=.bss
+FILE=DefaultBuild\r_main.obj
+                                  000fb500  000fc793      1294
+  _s_rb_fifo@2
+                                  000fb500       800   data ,l         * 
+  _g_app_runtime_job@5
+                                  000fbd00       290   data ,l         * 
+  _g_uart1_txbuf@7
+                                  000fbf90       400   data ,l         * 
+  _txbuf@18@forward_line_rs485_and_bridge@1
+                                  000fc390       404   data ,l         * 
+FILE=DefaultBuild\r_cg_serial.obj
+                                  000fc794  000fc7b3        20
+  _gp_uart0_tx_address
+                                  000fc794         2   data ,g         * 
+  _g_uart0_tx_count
+                                  000fc796         2   data ,g         * 
+  _gp_uart0_rx_address
+                                  000fc798         2   data ,g         * 
+  _g_uart0_rx_count
+                                  000fc79a         2   data ,g         * 
+  _g_uart0_rx_length
+                                  000fc79c         2   data ,g         * 
+  _gp_uart1_tx_address
+                                  000fc79e         2   data ,g         * 
+  _g_uart1_tx_count
+                                  000fc7a0         2   data ,g         * 
+  _gp_uart1_rx_address
+                                  000fc7a2         2   data ,g         * 
+  _g_uart1_rx_count
+                                  000fc7a4         2   data ,g         * 
+  _g_uart1_rx_length
+                                  000fc7a6         2   data ,g         * 
+  _g_iica0_master_status_flag
+                                  000fc7a8         1   data ,g         * 
+  _g_iica0_slave_status_flag
+                                  000fc7a9         1   data ,g         * 
+  _gp_iica0_rx_address
+                                  000fc7aa         2   data ,g         * 
+  _g_iica0_rx_len
+                                  000fc7ac         2   data ,g         * 
+  _g_iica0_rx_cnt
+                                  000fc7ae         2   data ,g         * 
+  _gp_iica0_tx_address
+                                  000fc7b0         2   data ,g         * 
+  _g_iica0_tx_cnt
+                                  000fc7b2         2   data ,g         * 
+FILE=DefaultBuild\i2c.obj
+                                  000fc7b4  000fcebe       70b
+  _rx@2@I2C_Command_Mode_Send
+                                  000fc7b4       258   data ,l         * 
+  _out@3@I2C_Command_Mode_Send
+                                  000fca0c       4b3   data ,l         * 
+FILE=DefaultBuild\uart.obj
+                                  000fcec0  000fd401       542
+  _s_uart1_txbuf@1
+                                  000fcec0       400   data ,l         * 
+  _s_uart0_txbuf@2
+                                  000fd2c0       140   data ,l         * 
+  _hex@4@uart1_send_hex
+                                  000fd400         2   data ,l         * 
+FILE=DefaultBuild\app_scheduler.obj
+                                  000fd402  000fe864      1463
+  _g_queue@1
+                                  000fd402      1460   data ,l         * 
+  _g_head@2
+                                  000fe862         1   data ,l         * 
+  _g_tail@3
+                                  000fe863         1   data ,l         * 
+  _g_count@4
+                                  000fe864         1   data ,l         * 
+FILE=DefaultBuild\app_owi_service.obj
+                                  000fe866  000fea69       204
+  _s_verified_long@1
+                                  000fe866        81   data ,l         * 
+  _samples@3@app_owi_read_verified_long@1
+                                  000fe8e7       183   data ,l         * 
+FILE=sprintf
+                                  000fea6a  000fea6d         4
+  __REL_pointer@1
+                                  000fea6a         4   data ,l         * 
+FILE=_REL_print
+                                  000fea6e  000feaed        80
+  _qt@1@_REL_inmod@1
+                                  000fea6e        80   data ,l         * 
+
+SECTION=.dataR
+FILE=DefaultBuild\r_main.obj
+                                  000feaee  000ff311       824
+  _uart_rx_done
+                                  000feaee         1   data ,g         * 
+  _uart_rx_index
+                                  000feaf0         2   data ,g         * 
+  _uart_rx_buffer
+                                  000feaf2       400   data ,g         * 
+  _uart_rx_length
+                                  000feef2         2   data ,g         * 
+  _rs485_rx_done
+                                  000feef4         1   data ,g         * 
+  _rs485_rx_index
+                                  000feef6         2   data ,g         * 
+  _rs485_rx_buffer
+                                  000feef8       400   data ,g         * 
+  _rs485_rx_length
+                                  000ff2f8         2   data ,g         * 
+  _g_uart0_err_fef
+                                  000ff2fa         4   data ,g         * 
+  _g_uart0_err_ovf
+                                  000ff2fe         4   data ,g         * 
+  _g_uart0_err_pef
+                                  000ff302         4   data ,g         * 
+  _g_rs485_bridge_active
+                                  000ff306         1   data ,g         * 
+  _g_rs485_bridge_done
+                                  000ff307         1   data ,g         * 
+  _g_rs485_bridge_seq
+                                  000ff308         2   data ,g         * 
+  _s_end_st@1
+                                  000ff30a         1   data ,l         * 
+  _g_fixed_addr
+                                  000ff30b         1   data ,g         * 
+  _s_rb_head@3
+                                  000ff30c         2   data ,l         * 
+  _s_rb_tail@4
+                                  000ff30e         2   data ,l         * 
+  _g_rs485_recover_streak@6
+                                  000ff310         1   data ,l         * 
+  _s_prefix_mode@8
+                                  000ff311         1   data ,l         * 
+FILE=DefaultBuild\owi.obj
+                                  000ff312  000ff31e         d
+  _bit_period_us@1
+                                  000ff312         4   data ,l         * 
+  _g_owi_timeout_latched@2
+                                  000ff316         1   data ,l         * 
+  _g_owi_last_timeout_byte_index@3
+                                  000ff318         2   data ,l         * 
+  _g_owi_last_timeout_bit_index@4
+                                  000ff31a         1   data ,l         * 
+  _g_owi_current_read_byte_index@5
+                                  000ff31c         2   data ,l         * 
+  _g_owi_current_read_bit_index@6
+                                  000ff31e         1   data ,l         * 
+FILE=DefaultBuild\i2c.obj
+                                  000ff320  000ff327         8
+  _i2c_tx_done
+                                  000ff320         1   data ,g         * 
+  _i2c_rx_done
+                                  000ff321         1   data ,g         * 
+  _g_i2c_last_command
+                                  000ff322         3   data ,g         * 
+  _g_i2c_command_valid
+                                  000ff325         1   data ,g         * 
+  _dis@1@disable
+                                  000ff326         2   data ,l         * 
+FILE=DefaultBuild\uart.obj
+                                  000ff328  000ff32d         6
+  _g_uart0_tx_done
+                                  000ff328         1   data ,g         * 
+  _g_uart1_tx_done
+                                  000ff329         1   data ,g         * 
+  _g_rs485_need_recover
+                                  000ff32a         1   data ,g         * 
+  _s_uart0_tx_len@3
+                                  000ff32c         2   data ,l         * 
+FILE=DefaultBuild\gatectrl.obj
+                                  000ff32e  000ff32e         1
+  _s_ch@1
+                                  000ff32e         1   data ,l         * 
+FILE=DefaultBuild\app_owi_service.obj
+                                  000ff330  000ff330         1
+  _s_verified_long_len@2
+                                  000ff330         1   data ,l         * 
+
+Absolute value symbols
+FILE=DefaultBuild\gatectrl.obj
+  @$IMM_28
+                                  00000028         0   none ,l         * 
+FILE=rlink_generates_05
+  __s.text
+                                  0000091b         0   none ,g         * 
+  __e.text
+                                  00000acc         0   none ,g         * 
+  __s.textf
+                                  0000361e         0   none ,g         * 
+  __e.textf
+                                  000074d8         0   none ,g         * 
+  __s.const
+                                  00003000         0   none ,g         * 
+  __e.const
+                                  0000361e         0   none ,g         * 
+  __s.constf
+                                  00000080         0   none ,g         * 
+  __e.constf
+                                  00000094         0   none ,g         * 
+  __s.data
+                                  000000d8         0   none ,g         * 
+  __e.data
+                                  0000091b         0   none ,g         * 
+  __s.sdata
+                                  00000080         0   none ,g         * 
+  __e.sdata
+                                  00000080         0   none ,g         * 
+  __s.bss
+                                  000fb500         0   none ,g         * 
+  __e.bss
+                                  000feaee         0   none ,g         * 
+  __s.sbss
+                                  000ffe20         0   none ,g         * 
+  __e.sbss
+                                  000ffe20         0   none ,g         * 
+  __s.dataR
+                                  000feaee         0   none ,g         * 
+  __e.dataR
+                                  000ff331         0   none ,g         * 
+  __s.sdataR
+                                  000ffe20         0   none ,g         * 
+  __e.sdataR
+                                  000ffe20         0   none ,g         * 
+  __s.init_array
+                                  00000094         0   none ,g         * 
+  __e.init_array
+                                  00000094         0   none ,g         * 
+  __s.RLIB
+                                  000000c4         0   none ,g         * 
+  __e.RLIB
+                                  000000c4         0   none ,g         * 
+  __s.SLIB
+                                  000074d8         0   none ,g         * 
+  __e.SLIB
+                                  00009de1         0   none ,g         * 
+  __s.option_byte
+                                  000000c0         0   none ,g         * 
+  __e.option_byte
+                                  000000c4         0   none ,g         * 
+  __s.monitor1
+                                  000000ce         0   none ,g         * 
+  __e.monitor1
+                                  000000d8         0   none ,g         * 
+  __s.monitor2
+                                  0003fe00         0   none ,g         * 
+  __e.monitor2
+                                  00040000         0   none ,g         * 
+  __s.security_id
+                                  000000c4         0   none ,g         * 
+  __e.security_id
+                                  000000ce         0   none ,g         * 
+  __s.vect
+                                  00000000         0   none ,g         * 
+  __e.vect
+                                  00000080         0   none ,g         * 
+  __RAM_ADDR_START
+                                  000faf00         0   none ,g         * 
+  __RAM_ADDR_END
+                                  000ffee0         0   none ,g         * 
+  __STACK_ADDR_START
+                                  000ffe20         0   none ,g         * 
+  __STACK_ADDR_END
+                                  000ff332         0   none ,g         * 
+
+*** Unfilled Areas ***
+
+AREA                                START    END
+
+*** Delete Symbols ***
+
+SYMBOL                                SIZE    INFO

QualityReport(multical,DefaultBuild).txt

@@ -0,0 +1,229 @@
+QualityReport
+2026년 8월 3일 월요일 오전 9:42:59
+
+------ Start build(multical, DefaultBuild) ------
+------ Build ended(Error:0, Warning:0)(multical, DefaultBuild) ------
+
+
+--- SHA1 hash value of output files ---
+C:\Users\temp\Desktop\new_fw - 115200\DefaultBuild\multical.abs: 018dff13bedabb61014296e2657d9cd501aa53f6
+C:\Users\temp\Desktop\new_fw - 115200\DefaultBuild\multical.mot: 284709bc9ae1a019ce30893e2f2b0f45c1e9828e
+
+
+--- System Information ---
+*OS Version
+ Microsoft Windows 10 Pro (-, 10.0.19045, WOW64)
+*Language
+ 한국어(대한민국)
+*.NET Framework Version
+ Microsoft .NET Framework 4 [.NET 4.8 or later] (533325)
+*WebView2 Version
+ 150.0.4078.105
+
+--- Application Information ---
+*Product Name
+ CS+ for CC
+*Package Version
+ V8.13.00  [05 Dec 2024]
+*Version
+ V9.13.00.05 [12 Nov 2024]
+*Assembly Version
+ 3.12.10.1
+*Product License
+ 
+*Execution Place
+ C:\Program Files (x86)\Renesas Electronics\CS+\CC
+*Memory Usage
+ *Private Working Set
+  287 MB
+ *Number of GDI Objects
+  2865
+ *Number of USER Objects
+  1602
+ *Opened Files
+  36 editors, 36 files, 257 KB
+
+--- Build Tool Plug-in Information ---
+RH850 Build tool CC-RH Plug-in
+ *Version
+  V8.09.00.00 [07 Oct 2022]
+ *Assembly Version
+  1.1.10.12
+ *DLL File Name
+  BuildToolCCRH.dll
+RL78 Build tool CC-RL Plug-in
+ *Version
+  V8.11.00.00 [29 Sep 2023]
+ *Assembly Version
+  1.0.0.0
+ *DLL File Name
+  BuildToolCCRL.dll
+RX Build tool CC-RX Plug-in
+ *Version
+  V8.09.00.00 [07 Oct 2022]
+ *Assembly Version
+  3.12.10.1
+ *DLL File Name
+  BuildToolCCRX.dll
+RH850 Build tool GHS CCRH850 Plug-in
+ *Version
+  V1.10.00.01 [25 Sep 2024]
+ *Assembly Version
+  1.0.0.0
+ *DLL File Name
+  BuildToolGHSCCRH850.dll
+
+--- Debug Tool Plug-in Information ---
+Debugger Collection Plug-in
+ *Version
+  V8.13.00.04 [26 Nov 2024]
+ *Assembly Version
+  2.12.10.1
+ *DLL File Name
+  DebugToolCollection.dll
+
+--- Other Plug-in Information ---
+Code Generator Plug-in for RH850
+ *Version
+  V1.02.02.05 [25 May 2018]
+ *Assembly Version
+  1.0.0.0
+ *DLL File Name
+  CodeGeneratorRH850.dll
+Code Generator Plug-in
+ *Version
+  V4.08.06.01 [28 Oct 2022]
+ *Assembly Version
+  3.0.0.0
+ *DLL File Name
+  CodePart.dll
+Code Generator/PinView Plug-in
+ *Version
+  V2.10.07.02 [08 Nov 2021]
+ *Assembly Version
+  1.0.0.0
+ *DLL File Name
+  CodePart2.dll
+Debug Console Plug-in
+ *Version
+  V8.09.00.03 [24 Nov 2022]
+ *Assembly Version
+  8.9.0.0
+ *DLL File Name
+  DebugConsole.dll
+Quick and Effective tool solution - QE
+ *Version
+  V9.12.00.01 [08 Apr 2024]
+ *Assembly Version
+  1.15.10.16
+ *DLL File Name
+  InCarTools.dll
+Pin Configurator Plug-in
+ *Version
+  V1.54.01.01 [31 Jul 2014]
+ *Assembly Version
+  1.6.10.23
+ *DLL File Name
+  PinConfig.dll
+Program Analyzer Plug-in
+ *Version
+  V4.13.00.03 [24 May 2023]
+ *Assembly Version
+  3.12.11.9
+ *DLL File Name
+  ProgramAnalyzer.dll
+IronPython Console Plug-in
+ *Version
+  V1.49.00.02 [08 Nov 2024]
+ *Assembly Version
+  1.6.10.23
+ *DLL File Name
+  PythonConsole.dll
+Editor plug-in DLL
+ *Version
+  V1.20.00.03 [20 May 2024]
+ *Assembly Version
+  1.1.0.0
+ *DLL File Name
+  SEditor.dll
+Stack Usage Tracer
+ *Version
+  V1.05.00.02 [30 Jul 2014]
+ *Assembly Version
+  1.30.11.15
+ *DLL File Name
+  Stk.dll
+Update Manager Plug-in
+ *Version
+  V2.03.00.02 [29 Oct 2018]
+ *Assembly Version
+  1.13.6.20
+ *DLL File Name
+  Update.dll
+
+Debug Tool Common Interface
+ *Version
+  V8.13.00.04 [26 Nov 2024]
+ *Assembly Version
+  3.12.10.1
+ *DLL File Name
+  CommonDebuggerInterface.dll
+Device Information Common Interface
+ *Version
+  V9.13.00.02 [03 Oct 2024]
+ *Assembly Version
+  3.0.0.0
+ *DLL File Name
+  DeviceInformation.dll
+
+--- Main Project Information ---
+C:\Users\temp\Desktop\new_fw - 115200\multical.mtpj
+Microcontroller Information
+ *R5F10PPJ
+  *File Name: Version
+   RL78_Productlist.xml: V8.130000
+   R5F10PPJ_common.xml: V1.13.00.XX.02
+   DR5F10PPJ.DVF: V1.11
+   f14_ppx.ti: V1.02
+   -: -
+  
+
+Build Tool Information
+ *CC-RL
+   * Version of plug-in(*.dll)
+     V8.13.00.02 [09 Oct 2024]
+   * The Version of the Compiler Package
+     V1.15.00
+  
+ * The version of SMS Assembler
+   V1.00.00.01 [29 May 2020]
+ * The version of GREEN_DSP Structured Assembler 
+   V1.05.00
+ 
+
+Debug Tool Information
+ *RL78 E1(Serial)
+  Debugger Library V8.13.00.04 [26 Nov 2024]
+  
+
+Other Tool Information
+ *None
+
+ *None
+
+ *None
+
+ *Pin Configurator
+ *Program Analyzer
+  *Version
+   V4.13.00.03 [24 May 2023]
+
+ *Code Generator
+Other Information
+ *RL78/F14 Code Library
+  *Version
+   V2.03.07.02 [08 Nov 2021]
+  *Description
+   Code library for RL78/F14 code generation plugin.
+
+

app_cmd_parser.c

@@ -0,0 +1,181 @@
+#include "app_cmd_parser.h"
+#include <string.h>
+#include <ctype.h>
+
+static int parse_x_v_addr(const char *line, uint8_t *addr)
+{
+    if (!line || !addr) return 0;
+    if (!(line[0] == 'x' || line[0] == 'X')) return 0;
+    if (!isdigit((unsigned char)line[1]) || !isdigit((unsigned char)line[2])) return 0;
+    if (!(line[3] == 'v' || line[3] == 'V')) return 0;
+    if (line[4] != '\0') return 0;
+
+    *addr = (uint8_t)((line[1] - '0') * 10 + (line[2] - '0'));
+    return 1;
+}
+
+static int find_payload_pos(const char *line)
+{
+    const char *p = strchr(line, ':');
+    if (!p) return -1;
+    return (int)(p - line + 1);
+}
+
+static uint8_t hex_nibble(char c)
+{
+    c = (char)toupper((unsigned char)c);
+    if (c >= '0' && c <= '9') return (uint8_t)(c - '0');
+    if (c >= 'A' && c <= 'F') return (uint8_t)(10 + (c - 'A'));
+    return 0xFFu;
+}
+
+static int hex_pair_to_u8(char hi, char lo, uint8_t *out)
+{
+    uint8_t h = hex_nibble(hi);
+    uint8_t l = hex_nibble(lo);
+    if (h == 0xFFu || l == 0xFFu || !out) return 0;
+    *out = (uint8_t)((h << 4) | l);
+    return 1;
+}
+
+int app_cmd_parse_line(app_cmd_src_t src, const char *line, app_job_t *job)
+{
+    uint8_t addr = 0;
+    int payload_pos;
+    int len;
+    int pos;
+    unsigned int k;
+
+    if (!line || !job) return 0;
+
+    memset(job, 0, sizeof(*job));
+    job->src = src;
+    job->check_on = 1;
+    
+    /* ?? ?? ?? ?? */
+    strncpy(job->line, line, sizeof(job->line) - 1);
+    job->line[sizeof(job->line) - 1] = '\0';
+
+    len = (int)strlen(line);
+
+    /* ?? ??*/
+    if (line[0] != 'x' && line[0] != 'X') {
+        job->type = APP_JOB_LOCAL_EXEC;
+        strncpy(job->line, line, sizeof(job->line) - 1);
+        job->line[sizeof(job->line) - 1] = '\0';
+        return 1;
+    }
+
+    /* xNNv */
+    if (parse_x_v_addr(line, &addr)) {
+        job->type = APP_JOB_SCAN_ADDR;
+        job->addr = addr;
+
+        strncpy(job->line, line, sizeof(job->line) - 1);
+        job->line[sizeof(job->line) - 1] = '\0';
+
+        return 1;
+    }
+
+    payload_pos = find_payload_pos(line);
+    if (payload_pos < 0) {
+        job->type = APP_JOB_FORWARD_LINE;
+        strncpy(job->line, line, sizeof(job->line) - 1);
+        job->line[sizeof(job->line) - 1] = '\0';
+        return 1;
+    }
+
+    if (len < payload_pos) return 0;
+    if (!isdigit((unsigned char)line[1]) || !isdigit((unsigned char)line[2])) return 0;
+
+    job->addr = (uint8_t)((line[1] - '0') * 10 + (line[2] - '0'));
+
+    /* xNNc_001101:... ±âÁØ¿¡¼­ channel = 001 */
+    if (payload_pos >= 8 &&
+        isdigit((unsigned char)line[5]) &&
+        isdigit((unsigned char)line[6]) &&
+        isdigit((unsigned char)line[7])) {
+        job->channel = (uint8_t)((line[5] - '0') * 100 +
+                                 (line[6] - '0') * 10 +
+                                 (line[7] - '0'));
+    }
+
+    job->mode = (char)toupper((unsigned char)line[3]);
+
+    if (payload_pos >= 11) {
+        job->hash_on   = (uint8_t)(line[8]  == '1');
+        job->anaout_on = (uint8_t)(line[9]  == '1');
+        job->check_on  = (uint8_t)(line[10] == '1');
+    }
+
+    pos = payload_pos;
+    if (pos + 1 >= len) return 0;
+
+    if ((line[pos] == 'o' || line[pos] == 'O') &&
+        (line[pos + 1] == 'w' || line[pos + 1] == 'W')) {
+        job->type = APP_JOB_PROTO_OW;
+        pos += 2;
+
+        if (pos < len && (line[pos] == 't' || line[pos] == 'T')) {
+            job->proto = APP_PROTO_OWIT;
+            pos++;
+        } else {
+            job->proto = APP_PROTO_OWIW;
+        }
+    }
+    else if ((line[pos] == 'o' || line[pos] == 'O') &&
+             (line[pos + 1] == 'r' || line[pos + 1] == 'R')) {
+        job->type = APP_JOB_PROTO_OR;
+        job->proto = APP_PROTO_OWIR;
+        pos += 2;
+    }
+    else {
+        job->type = APP_JOB_FORWARD_LINE;
+        strncpy(job->line, line, sizeof(job->line) - 1);
+        job->line[sizeof(job->line) - 1] = '\0';
+        return 1;
+    }
+
+    if (pos < len && (line[pos] == '_' || line[pos] == ':')) pos++;
+
+    if (pos + 1 >= len) return 0;
+    if (!hex_pair_to_u8(line[pos], line[pos + 1], &job->id)) return 0;
+    pos += 2;
+
+    if (pos + 2 >= len ||
+        !isdigit((unsigned char)line[pos]) ||
+        !isdigit((unsigned char)line[pos + 1]) ||
+        !isdigit((unsigned char)line[pos + 2])) {
+        return 0;
+    }
+
+    job->len = (uint16_t)(100 * (line[pos] - '0') +
+                           10 * (line[pos + 1] - '0') +
+                                (line[pos + 2] - '0'));
+    pos += 3;
+
+    if (job->type == APP_JOB_PROTO_OW) {
+        if (job->len == 0 || job->len > APP_JOB_PAYLOAD_MAX) return 0;
+        if (pos + ((int)job->len * 2) > len) return 0;
+
+        for (k = 0; k < job->len; k++) {
+            if (!hex_pair_to_u8(line[pos + (int)(2 * k)],
+                                line[pos + (int)(2 * k + 1)],
+                                &job->payload[k])) {
+                return 0;
+            }
+        }
+	    pos += (int)job->len * 2;
+
+	    /* payload ?? ??? ? ??? parse ?? */
+	    if (pos != len) return 0;
+
+	} else {
+	    if (job->len == 0 || job->len > APP_JOB_PAYLOAD_MAX) return 0;
+
+	    /* OR? payload? ??? ??? len ?? ?? ??? ? */
+	    if (pos != len) return 0;
+	}
+
+	return 1;
+}

app_cmd_parser.h

@@ -0,0 +1,8 @@
+#ifndef APP_CMD_PARSER_H
+#define APP_CMD_PARSER_H
+
+#include "app_types.h"
+
+int app_cmd_parse_line(app_cmd_src_t src, const char *line, app_job_t *job);
+
+#endif

app_owi_service.c

@@ -0,0 +1,221 @@
+#include "app_owi_service.h"
+#include "owi.h"
+#include "delay.h"
+#include "r_cg_wdt.h"
+#include <string.h>
+
+#define OWI_VERIFIED_MAX_LEN       129u
+#define OWI_VERIFIED_127_ATTEMPTS    6u
+#define OWI_VERIFIED_129_ATTEMPTS    8u
+#define OWI_VERIFIED_FIRST_US     30000u
+#define OWI_VERIFIED_RETRY_US     10000u
+
+static app_owi_result_t app_owi_from_raw(const owi_io_result_t *io)
+{
+    app_owi_result_t r;
+    uint16_t i;
+
+    memset(&r, 0, sizeof(r));
+
+    if (!io) {
+        r.ok = 0;
+        return r;
+    }
+
+    r.ok = io->ok;
+    r.timeout = io->timeout;
+    r.read_len = io->read_len;
+    r.timeout_byte_index = io->timeout_byte_index;
+    r.timeout_bit_index  = io->timeout_bit_index;
+
+    for (i = 0; i < io->read_len && i < OWI_IO_MAX_BYTES; i++) {
+        r.data[i] = io->data[i];
+    }
+
+    return r;
+}
+
+static uint8_t s_verified_long[OWI_VERIFIED_MAX_LEN];
+static uint8_t s_verified_long_len = 0u;
+
+static uint8_t is_long_owi_read(int length)
+{
+    return (length == 119) ? 1u : 0u;
+}
+
+static app_owi_result_t app_owi_read_verified_long(uint8_t id,
+                                                   uint8_t length,
+                                                   uint8_t max_attempts)
+{
+    static uint8_t samples[3][OWI_VERIFIED_MAX_LEN];
+    owi_io_result_t io;
+    uint8_t sample_count = 0u;
+    uint8_t attempt;
+    uint8_t sample;
+    uint8_t replace_index = 0u;
+
+    memset(&io, 0, sizeof(io));
+
+    for (attempt = 0u; attempt < max_attempts; attempt++) {
+        delay_us((attempt == 0u) ? OWI_VERIFIED_FIRST_US
+                                 : OWI_VERIFIED_RETRY_US);
+
+        R_WDT_Restart();
+        OWI_ReadBytesRaw((int)length, id, &io);
+        R_WDT_Restart();
+
+        if (!io.ok || io.timeout || io.read_len < length ||
+            io.data[0] != 0x26u) {
+            continue;
+        }
+
+        /* One fresh full read matching a previously verified value is enough. */
+        if (s_verified_long_len == length &&
+            memcmp(s_verified_long, io.data, length) == 0) {
+            return app_owi_from_raw(&io);
+        }
+
+        for (sample = 0u; sample < sample_count; sample++) {
+            if (memcmp(samples[sample], io.data, length) == 0) {
+                memcpy(s_verified_long, io.data, length);
+                s_verified_long_len = length;
+                return app_owi_from_raw(&io);
+            }
+        }
+
+        if (sample_count < 3u) {
+            memcpy(samples[sample_count], io.data, length);
+            sample_count++;
+        } else {
+            /* Keep recent distinct samples so a later stable pair can match. */
+            memcpy(samples[replace_index], io.data, length);
+            replace_index++;
+            if (replace_index >= 3u) {
+                replace_index = 0u;
+            }
+        }
+    }
+
+    /* Do not return a possibly corrupted long sample. */
+    memset(&io, 0, sizeof(io));
+    io.ok = 0u;
+    io.timeout = 1u;
+    io.timeout_byte_index = 0xFFFEu;
+    io.timeout_bit_index = 0xFEu;
+    return app_owi_from_raw(&io);
+}
+
+static uint8_t looks_bad_tail(const owi_io_result_t *io)
+{
+    uint16_t i;
+    uint8_t zero_run = 0;
+    uint8_t ff_run   = 0;
+
+    if (!io) return 1u;
+    if (io->read_len < 24u) return 1u;
+
+    for (i = (uint16_t)(io->read_len - 24u); i < io->read_len; i++) {
+        uint8_t b = io->data[i];
+
+        if (b == 0x00u) zero_run++;
+        else zero_run = 0;
+
+        if (b == 0xFFu) ff_run++;
+        else ff_run = 0;
+
+        /* tail ?? 8??? ?? ?? 00/FF? ??? */
+        if (zero_run >= 8u || ff_run >= 8u) {
+            return 1u;
+        }
+    }
+
+    return 0u;
+}
+
+/* ? ? ?? 4???? ?? 00 ?? ?? FF? ????? ?? */
+static uint8_t looks_bad_last_bytes(const owi_io_result_t *io)
+{
+    uint16_t start;
+    uint8_t i;
+    uint8_t all_zero = 1u;
+    uint8_t all_ff   = 1u;
+
+    if (!io) return 1u;
+    if (io->read_len < 3u) return 1u;
+
+    start = (uint16_t)(io->read_len - 3u);
+
+    for (i = 0; i < 3u; i++) {
+        uint8_t b = io->data[start + i];
+
+        if (b != 0x00u) all_zero = 0u;
+        if (b != 0xFFu) all_ff   = 0u;
+    }
+
+    return (uint8_t)(all_zero || all_ff);
+}
+
+static uint8_t needs_retry_for_long_read(const owi_io_result_t *io, int length)
+{
+    if (!is_long_owi_read(length)) return 0u;
+    if (!io) return 1u;
+
+    if (!io->ok) return 1u;
+    if (io->timeout) return 1u;
+    if (io->read_len < (uint16_t)length) return 1u;
+    if (looks_bad_tail(io)) return 1u;
+    if (looks_bad_last_bytes(io)) return 1u;
+
+    return 0u;
+}
+
+app_owi_result_t app_owi_read_basic(uint8_t id, int length)
+{
+    owi_io_result_t io;
+
+    if (length == 127) {
+        return app_owi_read_verified_long(id, 127u,
+                                          OWI_VERIFIED_127_ATTEMPTS);
+    }
+
+    if (length == 129) {
+        return app_owi_read_verified_long(id, 129u,
+                                          OWI_VERIFIED_129_ATTEMPTS);
+    }
+
+    R_WDT_Restart();
+    OWI_ReadBytesRaw(length, id, &io);
+    R_WDT_Restart();
+
+    if (needs_retry_for_long_read(&io, length)) {
+        R_WDT_Restart();
+        delay_us(3000u);
+        R_WDT_Restart();
+        OWI_ReadBytesRaw(length, id, &io);
+        R_WDT_Restart();
+
+        /* ??? ??? ???? ?? ?? */
+        if (needs_retry_for_long_read(&io, length)) {
+            io.ok = 0u;
+            io.timeout = 1u;
+            io.timeout_byte_index = 0xFFFEu;
+            io.timeout_bit_index  = 0xFEu;
+        }
+    }
+
+    return app_owi_from_raw(&io);
+}
+
+app_owi_result_t app_owi_write_basic(uint8_t id, const uint8_t *tx_data, uint8_t tx_len)
+{
+    owi_io_result_t io;
+    OWI_CommandModeRaw(tx_data, tx_len, id, &io);
+    return app_owi_from_raw(&io);
+}
+
+app_owi_result_t app_owi_write_t_basic(uint8_t id, const uint8_t *tx_data, uint8_t tx_len)
+{
+    owi_io_result_t io;
+    OWI_T_CommandModeRaw(tx_data, tx_len, id, &io);
+    return app_owi_from_raw(&io);
+}

app_owi_service.h

@@ -0,0 +1,20 @@
+#ifndef APP_OWI_SERVICE_H
+#define APP_OWI_SERVICE_H
+
+#include "r_cg_macrodriver.h"
+#include "owi.h"
+
+typedef struct {
+    uint8_t ok;
+    uint8_t timeout;
+    uint16_t read_len;
+    uint8_t data[OWI_IO_MAX_BYTES];
+    uint16_t timeout_byte_index;
+    uint8_t timeout_bit_index;
+} app_owi_result_t;
+
+app_owi_result_t app_owi_read_basic(uint8_t id, int length);
+app_owi_result_t app_owi_write_basic(uint8_t id, const uint8_t *tx_data, uint8_t tx_len);
+app_owi_result_t app_owi_write_t_basic(uint8_t id, const uint8_t *tx_data, uint8_t tx_len);
+
+#endif

app_result.c

@@ -0,0 +1,12 @@
+#include "app_result.h"
+#include "uart.h"
+
+void app_result_print_ok(const char *msg)
+{
+    uart1_send_string(msg);
+}
+
+void app_result_print_err(const char *msg)
+{
+    uart1_send_string(msg);
+}

app_result.h

@@ -0,0 +1,7 @@
+#ifndef APP_RESULT_H
+#define APP_RESULT_H
+
+void app_result_print_ok(const char *msg);
+void app_result_print_err(const char *msg);
+
+#endif

app_scheduler.c

@@ -0,0 +1,51 @@
+#include "app_scheduler.h"
+#include <string.h>
+
+#define APP_JOB_QUEUE_SIZE 8
+
+static app_job_t g_queue[APP_JOB_QUEUE_SIZE];
+static uint8_t g_head;
+static uint8_t g_tail;
+static uint8_t g_count;
+
+void app_scheduler_init(void)
+{
+    g_head = 0;
+    g_tail = 0;
+    g_count = 0;
+    memset(g_queue, 0, sizeof(g_queue));
+}
+
+int app_scheduler_push(const app_job_t *job)
+{
+    if (!job) return 0;
+    if (g_count >= APP_JOB_QUEUE_SIZE) return 0;
+
+    g_queue[g_tail] = *job;
+    g_tail = (uint8_t)((g_tail + 1U) % APP_JOB_QUEUE_SIZE);
+    g_count++;
+    return 1;
+}
+
+int app_scheduler_pop(app_job_t *job)
+{
+    if (!job) return 0;
+    if (g_count == 0) return 0;
+
+    *job = g_queue[g_head];
+    g_head = (uint8_t)((g_head + 1U) % APP_JOB_QUEUE_SIZE);
+    g_count--;
+    return 1;
+}
+
+int app_scheduler_is_empty(void)
+{
+    return (g_count == 0U);
+}
+void app_scheduler_clear(void)
+{
+    g_head = 0;
+    g_tail = 0;
+    g_count = 0;
+    memset(g_queue, 0, sizeof(g_queue));
+}

app_scheduler.h

@@ -0,0 +1,12 @@
+#ifndef APP_SCHEDULER_H
+#define APP_SCHEDULER_H
+
+#include "app_types.h"
+
+void app_scheduler_init(void);
+int  app_scheduler_push(const app_job_t *job);
+int  app_scheduler_pop(app_job_t *job);
+int  app_scheduler_is_empty(void);
+void app_scheduler_clear(void);
+
+#endif

app_types.h

@@ -0,0 +1,51 @@
+
+#ifndef APP_TYPES_H
+#define APP_TYPES_H
+
+#include "r_cg_macrodriver.h"
+
+#define APP_JOB_PAYLOAD_MAX 320
+#define APP_JOB_LINE_MAX    320
+
+typedef enum {
+    APP_CMD_SRC_PC = 0,
+    APP_CMD_SRC_RS485 = 1
+} app_cmd_src_t;
+
+typedef enum {
+    APP_JOB_NONE = 0,
+    APP_JOB_SCAN_ADDR,
+    APP_JOB_PROTO_OW,
+    APP_JOB_PROTO_OR,
+    APP_JOB_FORWARD_LINE,
+    APP_JOB_LOCAL_EXEC
+} app_job_type_t;
+
+typedef enum {
+    APP_PROTO_NONE = 0,
+    APP_PROTO_OWIW,
+    APP_PROTO_OWIT,
+    APP_PROTO_OWIR
+} app_proto_t;
+
+typedef struct {
+    app_job_type_t type;
+    app_cmd_src_t  src;
+
+    uint8_t        addr;
+    uint8_t        channel;
+    char           mode;
+    uint8_t        hash_on;
+    uint8_t        anaout_on;
+    uint8_t        check_on;
+
+    app_proto_t    proto;
+    uint8_t        id;
+    uint16_t       len;
+    uint8_t        payload[APP_JOB_PAYLOAD_MAX];
+
+    /* fallback¿ë ªÀº line¸¸ º¸°ü */
+    char           line[APP_JOB_LINE_MAX];
+} app_job_t;
+
+#endif

common.h

@@ -0,0 +1,4 @@
+#include "delay.h"
+#include "uart.h"
+#include "owi.h"
+#include "i2c.h"

cstart.asm

@@ -0,0 +1,314 @@
+;/**********************************************************************************************************************
+; * DISCLAIMER
+; * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+; * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+; * applicable laws, including copyright laws.
+; * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+; * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+; * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+; * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+; * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+; * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+; * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+; * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+; * following link:
+; * http://www.renesas.com/disclaimer
+; *
+; * Copyright (C) 2020-2022 Renesas Electronics Corporation. All rights reserved.
+; *********************************************************************************************************************/
+;   NOTE       : THIS IS A TYPICAL EXAMPLE.
+
+$IFNDEF __RENESAS_VERSION__
+__RENESAS_VERSION__	.EQU	0x01000000
+$ENDIF
+
+	.public	_start
+	.public _exit
+	.public _atexit
+
+;-----------------------------------------------------------------------------
+;	RAM section
+;-----------------------------------------------------------------------------
+.SECTION .dataR, DATA
+.SECTION .sdataR, DATA
+; .SECTION .datafR, DATAF
+; .SECTION .textfR, TEXTF
+
+$IF (__RENESAS_VERSION__ < 0x01010000)	; for CC-RL V1.00
+;-----------------------------------------------------------------------------
+;	stack area
+;-----------------------------------------------------------------------------
+; !!! [CAUTION] !!!
+; Set up stack size suitable for a project.
+.SECTION .stack_bss, BSS
+_stackend:
+	.DS     0x200
+_stacktop:
+$ENDIF
+
+;-----------------------------------------------------------------------------
+;	RESET vector
+;-----------------------------------------------------------------------------
+_start	.VECTOR	0
+
+;-----------------------------------------------------------------------------
+;	startup
+;-----------------------------------------------------------------------------
+.SECTION .text, TEXT
+_start:
+	;--------------------------------------------------
+	; setting register bank
+	;--------------------------------------------------
+;	SEL	RB0
+
+	;--------------------------------------------------
+	; setting mirror area
+	;--------------------------------------------------
+;	ONEB    !PMC		; mirror area = 10000-1FFFFH
+
+	;--------------------------------------------------
+	; setting the stack pointer
+	;--------------------------------------------------
+$IF (__RENESAS_VERSION__ >= 0x01010000)
+	MOVW	SP,#LOWW(__STACK_ADDR_START)
+$ELSE	; for CC-RL V1.00
+	MOVW	SP,#LOWW(_stacktop)
+$ENDIF
+
+	;--------------------------------------------------
+	; initializing stack area
+	;--------------------------------------------------
+$IF (__RENESAS_VERSION__ >= 0x01010000)
+	MOVW	AX,#LOWW(__STACK_ADDR_END)
+$ELSE	; for CC-RL V1.00
+	MOVW	AX,#LOWW(_stackend)
+$ENDIF
+	CALL	!!_stkinit
+
+	;--------------------------------------------------
+	; hardware initialization
+	;--------------------------------------------------
+	CALL	!!_hdwinit
+
+$IFDEF __USE_RAM_INIT_TABLE
+	;--------------------------------------------------
+	; initializing RAM
+	;--------------------------------------------------
+	MOVW	AX,#LOWW(STARTOF(.ram_init_table))
+	BR	$.L5_RAM_INIT_TABLE
+.L1_RAM_INIT_TABLE:
+	PUSH	AX		;table pointer
+	MOVW	HL,AX
+	MOV	ES,#HIGHW(STARTOF(.ram_init_table))
+	MOVW	AX,ES:[HL+6]	;dst
+	MOVW	DE,AX
+	MOVW	AX,ES:[HL+4]	;size
+	ADDW	AX,DE
+	MOVW	BC,AX		;end
+	MOV	A,ES:[HL+2]	;high(src)
+	CMP	A,#0xF
+	BZ	$.L3_RAM_INIT_TABLE_CLEAR
+
+	PUSH	AX
+	MOVW	AX,ES:[HL]	;loww(src)
+	MOVW	HL,AX
+	POP	AX
+	MOV	ES,A
+	BR	$.L3_RAM_INIT_TABLE_COPY
+
+.L2_RAM_INIT_TABLE_COPY:
+	MOV	A,ES:[HL]
+	INCW	HL
+	MOV	[DE],A
+	INCW	DE
+.L3_RAM_INIT_TABLE_COPY:
+	MOVW	AX,DE
+	CMPW	AX,BC
+	BC	$.L2_RAM_INIT_TABLE_COPY
+	BR	$.L4_RAM_INIT_TABLE
+
+.L2_RAM_INIT_TABLE_CLEAR:
+	MOV	[DE],#0
+	INCW	DE
+.L3_RAM_INIT_TABLE_CLEAR:
+	MOVW	AX,DE
+	CMPW	AX,BC
+	BC	$.L2_RAM_INIT_TABLE_CLEAR
+
+.L4_RAM_INIT_TABLE:
+	POP	AX		;table ponter
+	ADDW	AX,#8
+.L5_RAM_INIT_TABLE:
+	CMPW	AX,#LOWW(STARTOF(.ram_init_table)+SIZEOF(.ram_init_table))
+	BC	$.L1_RAM_INIT_TABLE
+
+$ELSE	; __USE_RAM_INIT_TABLE
+	;--------------------------------------------------
+	; initializing BSS
+	;--------------------------------------------------
+	; clear external variables which doesn't have initial value (near)
+	MOVW	HL,#LOWW(STARTOF(.bss))
+	MOVW	AX,#LOWW(STARTOF(.bss) + SIZEOF(.bss))
+	BR	$.L2_BSS
+.L1_BSS:
+	MOV	[HL+0],#0
+	INCW	HL
+.L2_BSS:
+	CMPW	AX,HL
+	BNZ	$.L1_BSS
+
+	; clear saddr variables which doesn't have initial value
+	MOVW	HL,#LOWW(STARTOF(.sbss))
+	MOVW	AX,#LOWW(STARTOF(.sbss) + SIZEOF(.sbss))
+	BR	$.L2_SBSS
+.L1_SBSS:
+	MOV	[HL+0],#0
+	INCW	HL
+.L2_SBSS:
+	CMPW	AX,HL
+	BNZ	$.L1_SBSS
+
+	; clear external variables which doesn't have initial value (far)
+;	MOV	ES,#HIGHW(STARTOF(.bssf))
+;	MOVW	HL,#LOWW(STARTOF(.bssf))
+;	MOVW	AX,#LOWW(STARTOF(.bssf) + SIZEOF(.bssf))
+;	BR	$.L2_BSSF
+;.L1_BSSF:
+;	MOV	ES:[HL+0],#0
+;	INCW	HL
+;.L2_BSSF:
+;	CMPW	AX,HL
+;	BNZ	$.L1_BSSF
+
+	;--------------------------------------------------
+	; ROM data copy
+	;--------------------------------------------------
+	; copy external variables having initial value (near)
+	MOV	ES,#HIGHW(STARTOF(.data))
+	MOVW	BC,#LOWW(SIZEOF(.data))
+	BR	$.L2_DATA
+.L1_DATA:
+	DECW	BC
+	MOV	A,ES:LOWW(STARTOF(.data))[BC]
+	MOV	LOWW(STARTOF(.dataR))[BC],A
+.L2_DATA:
+	CLRW	AX
+	CMPW	AX,BC
+	BNZ	$.L1_DATA
+
+	; copy saddr variables having initial value
+	MOV	ES,#HIGHW(STARTOF(.sdata))
+	MOVW	BC,#LOWW(SIZEOF(.sdata))
+	BR	$.L2_SDATA
+.L1_SDATA:
+	DECW	BC
+	MOV	A,ES:LOWW(STARTOF(.sdata))[BC]
+	MOV	LOWW(STARTOF(.sdataR))[BC],A
+.L2_SDATA:
+	CLRW	AX
+	CMPW	AX,BC
+	BNZ	$.L1_SDATA
+
+	; copy external variables having initial value (far)
+;	MOVW	BC,#LOWW(SIZEOF(.dataf))
+;	BR	$.L2_DATAF
+;.L1_DATAF:
+;	DECW	BC
+;	MOV	ES,#HIGHW(STARTOF(.dataf))
+;	MOV	A,ES:LOWW(STARTOF(.dataf))[BC]
+;	MOV	ES,#HIGHW(STARTOF(.datafR))
+;	MOV	ES:LOWW(STARTOF(.datafR))[BC],A
+;.L2_DATAF:
+;	CLRW	AX
+;	CMPW	AX,BC
+;	BNZ	$.L1_DATAF
+
+	; copy .text to RAM
+;	MOV	C,#HIGHW(STARTOF(.textf))
+;	MOVW	HL,#LOWW(STARTOF(.textf))
+;	MOVW	DE,#LOWW(STARTOF(.textfR))
+;	BR	$.L2_TEXT
+;.L1_TEXT:
+;	MOV	A,C
+;	MOV	ES,A
+;	MOV	A,ES:[HL]
+;	MOV	[DE],A
+;	INCW	DE
+;	INCW	HL
+;	CLRW	AX
+;	CMPW	AX,HL
+;	SKNZ
+;	INC	C
+;.L2_TEXT:
+;	MOVW	AX,HL
+;	CMPW	AX,#LOWW(STARTOF(.text) + SIZEOF(.text))
+;	BNZ	$.L1_TEXT
+
+$ENDIF	; __USE_RAM_INIT_TABLE
+
+	;--------------------------------------------------
+	; call global constructor (_peace_global_ctor_0)
+	;--------------------------------------------------
+	MOVW	BC,#LOWW(SIZEOF(.init_array))
+	BR	$.L2_INIT
+.L1_INIT:
+	DECW	BC
+	DECW	BC
+	MOV	ES,#HIGHW(STARTOF(.init_array))
+	MOVW	AX,ES:LOWW(STARTOF(.init_array))[BC]
+	MOV	CS,#0x00
+	PUSH	BC
+	CALL	AX
+	POP	BC
+.L2_INIT:
+	CLRW	AX
+	CMPW	AX,BC
+	BNZ	$.L1_INIT
+
+	;--------------------------------------------------
+	; call main function
+	;--------------------------------------------------
+	CALL	!!_main		; main();
+
+	;--------------------------------------------------
+	; call exit function
+	;--------------------------------------------------
+	CLRW	AX		; exit(0)
+_exit:
+	BR	$_exit
+
+;-----------------------------------------------------------------------------
+;	atexit (only ret)
+;-----------------------------------------------------------------------------
+_atexit:
+	RET
+
+;-----------------------------------------------------------------------------
+;	section
+;-----------------------------------------------------------------------------
+$IF (__RENESAS_VERSION__ >= 0x01010000)
+.SECTION .RLIB, TEXTF
+.L_section_RLIB:
+.SECTION .SLIB, TEXTF
+.L_section_SLIB:
+$ENDIF
+.SECTION .textf, TEXTF
+.L_section_textf:
+.SECTION .const, CONST
+.L_section_const:
+.SECTION .constf, CONSTF
+.L_section_constf:
+.SECTION .data, DATA
+.L_section_data:
+;.SECTION .dataf, DATAF
+;.L_section_dataf:
+.SECTION .sdata, SDATA
+.L_section_sdata:
+.SECTION .bss, BSS
+.L_section_bss:
+;.SECTION .bssf, BSSF
+;.L_section_bssf:
+.SECTION .sbss, SBSS
+.L_section_sbss:
+.SECTION .init_array, CONSTF
+.L_section_init_array:

delay.c

@@ -0,0 +1,86 @@
+#include "delay.h"
+
+
+/**
+ * 함수명: delay
+ * 목적: 단순 루프를 이용한 지연(delay) 함수
+ *
+ * 매개변수:
+ *   - d : 지연 카운트 값. 값이 클수록 지연 시간이 길어짐
+ *
+ * 동작 방식:
+ *   - while(d--) 루프를 반복하면서 CPU를 바쁘게 사용
+ *   - 외부 타이머나 정확한 시간 기준은 없음
+ *   - 단순히 CPU 사이클을 소비하여 지연 발생
+ *
+ * 주의사항:
+ *   - CPU 클럭에 따라 지연 시간이 달라짐
+ *   - 정밀한 시간 지연이 필요하면 하드웨어 타이머 사용 권장
+ */
+void delay(long d){
+ while(d--);	
+}
+
+
+/**
+ * 함수명: delay_us
+ * 목적: 마이크로초(us) 단위의 지연(delay) 함수
+ *
+ * 매개변수:
+ *   - us : 지연 시간 (마이크로초 단위)
+ *
+ * 동작 방식:
+ *   1. 입력된 us 값에 따라 반복 횟수 count 계산
+ *      - us <= 150 : count = (us * 100 + 50) / 100
+ *      - us > 150 : count = (us * 106 + 50) / 100
+ *      - 소수점 올림 효과를 위해 +50 추가
+ *   2. for 루프를 count만큼 반복하면서 __nop() 수행
+ *      - __nop()는 "No Operation" 명령어로, CPU 사이클만 소비
+ *   3. 루프 종료 후 지정된 시간만큼 지연
+ *
+ * 주의사항:
+ *   - CPU 클럭 속도에 따라 실제 지연 시간은 달라질 수 있음
+ *   - 매우 정밀한 시간 지연이 필요하면 타이머 기반 지연 권장
+ */
+void delay_us(volatile uint32_t us)
+{
+    volatile uint32_t i;
+    volatile uint32_t count;
+
+    if (us <= 150) {
+    count = (us * 100 + 50) / 100;  // 소수점 올림 효과를 위해 +50 추가
+	} else {
+	    count = (us * 106 + 50) / 100;
+	}
+
+    for (i = 0; i < count; i++) {
+        __nop();
+    }
+}
+
+
+/**
+ * 함수명: delay_ms
+ * 목적: 밀리초(ms) 단위의 지연(delay) 함수
+ *
+ * 매개변수:
+ *   - ms : 지연 시간 (밀리초 단위)
+ *
+ * 동작 방식:
+ *   1. 외부 for 루프(i)는 ms만큼 반복
+ *   2. 내부 for 루프(j)는 0~799까지 반복
+ *      - 내부 루프 반복 횟수 800은 CPU 클럭 속도에 따라 조정 필요
+ *      - 반복 동안 아무 작업도 하지 않고 CPU 사이클 소모
+ *   3. 두 루프가 모두 끝나면 지정된 시간만큼 대략 지연 완료
+ *
+ * 주의사항:
+ *   - 정확한 시간 지연은 보장되지 않음 (CPU 클럭, 최적화 레벨 등 영향)
+ *   - 매우 정밀한 지연이 필요하면 타이머 기반 지연 권장
+ *   - delay_ms와 delay_us를 혼합해 사용할 수 있음
+ */
+void delay_ms(unsigned int ms)
+{
+    volatile unsigned int i, j;
+    for (i = 0; i < ms; i++)
+        for (j = 0; j < 800; j++);  // 내부 루프 조정 필요 (클럭에 따라 조정)
+}

delay.h

@@ -0,0 +1,5 @@
+#include "r_cg_macrodriver.h"
+
+void delay(long d);
+void delay_ms(unsigned int ms);
+void delay_us(volatile uint32_t us);

dipSwitch.c

@@ -0,0 +1,32 @@
+#include "dipSwitch.h"
+
+/*
+ * 회로도 기준:
+ * ADD_1..ADD_5 = P8.1..P8.5
+ * Pull-up to VCC5, DIP ON -> GND(LOW) => Active-Low
+ */
+#define DIP_PORT   P8
+#define DIP_PM     PM8
+#define DIP_MASK   (0x3Eu)   // b0011_1110 = P8.1~P8.5
+#define DIP_SHIFT  (1u)      // P8.1이 bit0로 오도록
+
+void DipSwitch_Init(void)
+{
+    // 입력 설정: PM bit=1 => input
+    DIP_PM |= DIP_MASK;
+}
+
+uint8_t DipSwitch_ReadAddr_0to31(void)
+{
+    uint8_t raw = (uint8_t)(DIP_PORT & DIP_MASK);
+
+    // Active-Low이므로 반전 후, 마스크 적용
+    uint8_t v = (uint8_t)((~raw) & DIP_MASK);
+
+    // P8.1~P8.5 -> bit0~bit4
+    v = (uint8_t)(v >> DIP_SHIFT);
+
+    return (uint8_t)(v & 0x1Fu); // 0~31
+}
+
+

dipSwitch.h

@@ -0,0 +1,32 @@
+#ifndef DIPSWITCH_H
+#define DIPSWITCH_H
+
+#include "r_cg_macrodriver.h"
+#include "r_cg_port.h"   // P8, PM8 사용
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * DIP Switch 초기화 (입력 설정)
+ */
+void DipSwitch_Init(void);
+
+/**
+ * DIP Switch(5bit)를 읽어 주소(1~32)로 변환해 반환
+ * - 회로: Pull-up, DIP ON -> GND (Active-Low)
+ * - 핀: P8.1~P8.5 (ADD_1~ADD_5)
+ */
+
+/**
+ * (옵션) 디버그용: DIP 5bit(0~31) 그대로 반환
+ * - ADD_1이 LSB
+ */
+uint8_t DipSwitch_ReadAddr_0to31(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DIPSWITCH_H */

gatectrl.c

@@ -0,0 +1,173 @@
+#include "gatectrl.h"
+
+static uint8_t s_ch = 1;
+
+#define PORT_BIT_SETCLR(PORT, MASK, ON)            \
+    do {                                           \
+        if (ON) { (PORT) |=  (uint8_t)(MASK); }    \
+        else     { (PORT) &= (uint8_t)~(MASK); }   \
+    } while (0)
+
+void Gate_SetByNum(uint8_t ch, uint8_t hash_on, uint8_t anaout_on, uint8_t check_on)
+{
+    switch (ch)
+    {
+        case 1: /* HASH P15.3, ANAOUT P6.4, CHECK P15.4 */
+            PORT_BIT_SETCLR(P15, 0x08, hash_on);    // P15.3
+            PORT_BIT_SETCLR(P6,  0x10, anaout_on);  // P6.4
+            PORT_BIT_SETCLR(P15, 0x10, check_on);   // P15.4
+            break;
+
+        case 2: /* P15.2, P6.5, P15.5 */
+            PORT_BIT_SETCLR(P15, 0x04, hash_on);    // P15.2
+            PORT_BIT_SETCLR(P6,  0x20, anaout_on);  // P6.5
+            PORT_BIT_SETCLR(P15, 0x20, check_on);   // P15.5
+            break;
+
+        case 3: /* P15.1, P6.6, P0.0 */
+            PORT_BIT_SETCLR(P15, 0x02, hash_on);    // P15.1
+            PORT_BIT_SETCLR(P6,  0x40, anaout_on);  // P6.6
+            PORT_BIT_SETCLR(P0,  0x01, check_on);   // P0.0
+            break;
+
+        case 4: /* P15.0, P6.7, P15.6 */
+            PORT_BIT_SETCLR(P15, 0x01, hash_on);    // P15.0
+            PORT_BIT_SETCLR(P6,  0x80, anaout_on);  // P6.7
+            PORT_BIT_SETCLR(P15, 0x40, check_on);   // P15.6
+            break;
+
+        case 5: /* P12.0, P4.4, P3.0 */
+            PORT_BIT_SETCLR(P12, 0x01, hash_on);    // P12.0
+            PORT_BIT_SETCLR(P4,  0x10, anaout_on);  // P4.4
+            PORT_BIT_SETCLR(P3,  0x01, check_on);   // P3.0
+            break;
+
+        case 6: /* P12.5, P4.3, P3.2 */
+            PORT_BIT_SETCLR(P12, 0x20, hash_on);    // P12.5
+            PORT_BIT_SETCLR(P4,  0x08, anaout_on);  // P4.3
+            PORT_BIT_SETCLR(P3,  0x04, check_on);   // P3.2
+            break;
+
+        case 7: /* P0.1, P4.2, P0.3 */
+            PORT_BIT_SETCLR(P0,  0x02, hash_on);    // P0.1
+            PORT_BIT_SETCLR(P4,  0x04, anaout_on);  // P4.2
+            PORT_BIT_SETCLR(P0,  0x08, check_on);   // P0.3
+            break;
+
+        case 8: /* P12.6, P4.1, P7.0 */
+            PORT_BIT_SETCLR(P12, 0x40, hash_on);    // P12.6
+            PORT_BIT_SETCLR(P4,  0x02, anaout_on);  // P4.1
+            PORT_BIT_SETCLR(P4,  0x40, check_on);   // P7.0 -> p4.6으로 변경
+            break;
+
+        case 9: /* P12.7, P5.0, P7.1 */
+            PORT_BIT_SETCLR(P12, 0x80, hash_on);    // P12.7
+            PORT_BIT_SETCLR(P5,  0x01, anaout_on);  // P5.0
+            PORT_BIT_SETCLR(P7,  0x02, check_on);   // P7.1
+            break;
+
+        case 10: /* P0.2, P5.1, P10.4 */
+            PORT_BIT_SETCLR(P0,  0x04, hash_on);    // P0.2
+            PORT_BIT_SETCLR(P5,  0x02, anaout_on);  // P5.1
+            PORT_BIT_SETCLR(P10, 0x10, check_on);   // P10.4
+            break;
+
+	case 11: /* P9.2, P13.0, P1.4 */
+	    PORT_BIT_SETCLR(P9,  0x04, hash_on);    // P9.2
+	    PORT_BIT_SETCLR(P13, 0x01, anaout_on);  // P13.0
+	    PORT_BIT_SETCLR(P1,  0x10, check_on);   // P1.4
+	    break;
+
+	case 12: /* P9.3, P7.7, P1.3 */
+	    PORT_BIT_SETCLR(P9,  0x08, hash_on);    // P9.3
+	    PORT_BIT_SETCLR(P7,  0x80, anaout_on);  // P7.7
+	    PORT_BIT_SETCLR(P1,  0x08, check_on);   // P1.3
+	    break;
+
+	case 13: /* P9.4, P7.6, P1.0 */
+	    PORT_BIT_SETCLR(P9,  0x10, hash_on);    // P9.4
+	    PORT_BIT_SETCLR(P7,  0x40, anaout_on);  // P7.6
+	    PORT_BIT_SETCLR(P1,  0x01, check_on);   // P1.0
+	    break;
+
+	case 14: /* P9.5, P7.4, P5.4 */
+	    PORT_BIT_SETCLR(P9,  0x20, hash_on);    // P9.5
+	    PORT_BIT_SETCLR(P7,  0x10, anaout_on);  // P7.4
+	    PORT_BIT_SETCLR(P5,  0x10, check_on);   // P5.4
+	    break;
+
+	case 15: /* P9.6, P7.5, P5.5 */
+	    PORT_BIT_SETCLR(P9,  0x40, hash_on);    // P9.6
+	    PORT_BIT_SETCLR(P7,  0x20, anaout_on);  // P7.5
+	    PORT_BIT_SETCLR(P5,  0x20, check_on);   // P5.5
+	    break;
+
+	case 16: /* P9.7, P7.3, P5.6 */
+	    PORT_BIT_SETCLR(P9,  0x80, hash_on);    // P9.7
+	    PORT_BIT_SETCLR(P7,  0x08, anaout_on);  // P7.3
+	    PORT_BIT_SETCLR(P5,  0x40, check_on);   // P5.6
+	    break;
+
+	case 17: /* P10.0, P7.2, P5.7 */
+	    PORT_BIT_SETCLR(P10, 0x01, hash_on);    // P10.0
+	    PORT_BIT_SETCLR(P7,  0x04, anaout_on);  // P7.2
+	    PORT_BIT_SETCLR(P5,  0x80, check_on);   // P5.7
+	    break;
+
+	case 18: /* P10.1, P6.1, P10.7 */
+	    PORT_BIT_SETCLR(P10, 0x02, hash_on);    // P10.1
+	    PORT_BIT_SETCLR(P6,  0x02, anaout_on);  // P6.1
+	    PORT_BIT_SETCLR(P10, 0x80, check_on);   // P10.7
+	    break;
+
+	case 19: /* P10.2, P6.0, P10.6 */
+	    PORT_BIT_SETCLR(P10, 0x04, hash_on);    // P10.2
+	    PORT_BIT_SETCLR(P6,  0x01, anaout_on);  // P6.0
+	    PORT_BIT_SETCLR(P10, 0x40, check_on);   // P10.6
+	    break;
+
+	case 20: /* P10.3, P5.2, P10.5 */
+	    PORT_BIT_SETCLR(P10, 0x08, hash_on);    // P10.3
+	    PORT_BIT_SETCLR(P5,  0x04, anaout_on);  // P5.2
+	    PORT_BIT_SETCLR(P10, 0x20, check_on);   // P10.5
+    break;
+
+
+        default:
+            break;
+    }
+}
+
+void Cal_Init(void)
+{
+    uint8_t i;
+
+    // P4.7 = 0, P15.7 = 1 (다른 비트 보존!)
+    PORT_BIT_SETCLR(P4,  0x80, 0);
+    PORT_BIT_SETCLR(P15, 0x80, 1);
+
+    for (i = 1; i <= 20; i++) {
+        Gate_SetByNum(i, 0, 0, 1);  // hash=0, anaout=0, check=1
+    }
+}
+
+void Eol_Init(void)
+{
+    uint8_t i;
+
+    // P4.7 = 1, P15.7 = 0 (다른 비트 보존!)
+    PORT_BIT_SETCLR(P4,  0x80, 1);
+    PORT_BIT_SETCLR(P15, 0x80, 1);
+
+    for (i = 1; i <= 20; i++) {
+        Gate_SetByNum(i, 0, 0, 1);  // hash=0, anaout=0, check=1
+    }
+}
+
+void GateCtrl_SelectChannel(uint8_t ch)
+{
+    if (ch < 1 || ch > 20) return;
+    s_ch = ch;
+}
+
+

gatectrl.h

@@ -0,0 +1,15 @@
+#ifndef GATECTRL_H
+#define GATECTRL_H
+
+#include "r_cg_macrodriver.h"
+#include "r_cg_port.h"
+#include <stdint.h>
+
+void Gate_SetByNum(uint8_t ch, uint8_t hash_on, uint8_t anaout_on, uint8_t check_on);
+
+void Cal_Init(void);
+void Eol_Init(void);
+
+void GateCtrl_SelectChannel(uint8_t ch);
+
+#endif

hdwinit.asm

@@ -0,0 +1,35 @@
+;/**********************************************************************************************************************
+; * DISCLAIMER
+; * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+; * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+; * applicable laws, including copyright laws.
+; * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+; * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+; * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+; * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+; * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+; * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+; * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+; * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+; * following link:
+; * http://www.renesas.com/disclaimer
+; *
+; * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+; *********************************************************************************************************************/;---------------------------------------------------------------------
+;	_hdwinit
+;
+;	void _hdwinit(void);
+;
+;	input:
+;		NONE
+;	output:
+;		NONE
+;---------------------------------------------------------------------
+
+;   NOTE       : THIS IS A TYPICAL EXAMPLE.
+
+	.PUBLIC	_hdwinit
+
+.textf	.CSEG	TEXTF
+_hdwinit:
+	RET

i2c.c

@@ -0,0 +1,253 @@
+#include "i2c.h"
+#include "delay.h"
+#include "uart.h"
+#include <string.h>
+
+volatile uint8_t i2c_tx_done = 0;
+volatile uint8_t i2c_rx_done = 0;
+
+uint8_t g_i2c_last_command[3] = {0};
+uint8_t g_i2c_command_valid = 0;
+
+
+/**
+ * 함수명: disable
+ * 목적: I2C 장치에 비활성화(disable) 명령을 전송
+ *
+ * 매개변수: 없음
+ *
+ * 반환값: 없음 (void)
+ *
+ * 동작 방식:
+ *   1) 전송할 데이터 준비
+ *      - dis 배열에 {0x01, 0x02} 값 저장
+ *
+ *   2) I2C 송신
+ *      - R_IICA0_Master_Send() 호출하여 슬레이브 주소로 데이터 전송
+ *      - 전송 성공 시 다음 단계로 진행
+ *      - 전송 실패 시 UART로 "I2C Send Failed" 메시지 출력 후 함수 종료
+ *
+ * 참고:
+ *   - SLAVE_ADDR는 전송 대상 I2C 장치 주소
+ *   - sizeof(dis)를 통해 전송할 데이터 길이 자동 계산
+ *   - 전송 타임아웃은 100ms
+ */
+void disable(void){
+    static uint8_t dis[] = {0x01, 0x02};
+    //static uint8_t tx[] = {0xT0, 0x00, 0x00};
+    
+    // I2C 마스터 송신
+    if (R_IICA0_Master_Send(SLAVE_ADDR << 1, dis, sizeof(dis), 100) != MD_OK)
+    {
+        HOST_PRINT("I2C Send Failed\r\n");
+        return;
+    }
+}
+
+
+/**
+ * 함수명: I2C_EnablePower
+ * 목적: I2C 장치 전원을 켠다.
+ *
+ * 매개변수: 없음
+ *
+ * 반환값: 없음 (void)
+ *
+ * 동작 방식:
+ *   1) P7 레지스터의 특정 비트를 설정하여 전원 출력 HIGH 상태로 변경
+ *      - _02_Pn1_OUTPUT_1 : P7 포트의 1번 핀을 출력 모드로 HIGH 설정
+ *
+ * 참고:
+ *   - I2C 장치 전원 공급용 핀을 제어
+ *   - 출력 HIGH 상태로 전원이 켜짐
+ */
+void I2C_EnablePower(void) {
+    P7 = _02_Pn1_OUTPUT_1;
+}
+
+
+/**
+ * 함수명: I2C_DisablePower
+ * 목적: I2C 장치 전원을 끈다.
+ *
+ * 매개변수: 없음
+ *
+ * 반환값: 없음 (void)
+ *
+ * 동작 방식:
+ *   1) P7 레지스터의 특정 비트를 클리어하여 전원 출력 LOW 상태로 변경
+ *      - _00_Pn1_OUTPUT_0 : P7 포트의 1번 핀을 출력 모드로 LOW 설정
+ *
+ * 참고:
+ *   - I2C 장치 전원 공급용 핀을 제어
+ *   - 출력 LOW 상태로 전원이 꺼짐
+ */
+void I2C_DisablePower(void) {
+    P7 = _00_Pn1_OUTPUT_0;
+}
+
+
+/**
+ * 함수명: I2C_T_Command_Mode_receiveData
+ * 목적: I2C 장치에 명령(tx_data) 전송 후, 상태를 UART로 출력
+ *
+ * 매개변수:
+ *   - tx_data : I2C로 전송할 데이터 버퍼
+ *   - tx_len  : 전송할 데이터 길이 (바이트)
+ *   - id      : I2C 슬레이브 장치 주소
+ *
+ * 반환값: 없음 (void)
+ *
+ * 동작 방식:
+ *   1) I2C 하드웨어 초기화
+ *      - R_IICA0_Create()를 호출하여 I2C 모듈 초기화
+ *      - I2C 장치에 전원 공급 (I2C_EnablePower())
+ *      - 전원 안정화를 위해 약간의 delay(1초)
+ *
+ *   2) I2C 명령 전송
+ *      - R_IICA0_Master_Send()로 장치에 tx_data 전송
+ *      - 전송 실패 시 UART로 "I2C Send Failed" 출력하고 함수 종료
+ *
+ *   3) UART 출력
+ *      - 전송 성공 여부와 상관없이 "51" 문자열을 UART로 출력
+ *
+ * 참고:
+ *   - 이 함수는 읽기(read) 기능 없이 명령 전송만 수행
+ *   - UART 출력 "51"은 전송 완료 신호/디버깅용
+ */
+void I2C_T_Command_Mode_receiveData(const uint8_t *tx_data, uint8_t tx_len,uint8_t id )
+{
+    char uart_buf[16];
+    int j;
+    uint8_t rx[3] = {0};	
+
+    R_IICA0_Create();
+    I2C_EnablePower();
+    delay(10000);
+
+    if (R_IICA0_Master_Send((id << 1), tx_data, tx_len, 100) != MD_OK)
+    {
+        HOST_PRINT("I2C Send Failed\r\n");
+        return;
+    }
+
+ 
+    HOST_PRINT("51\r\n");
+    
+
+
+    
+}
+
+
+/**
+ * 함수명: I2C_Command_Mode_receiveData
+ * 목적: I2C 장치에 명령(tx_data)을 전송하고, 상태를 UART로 출력
+ *
+ * 매개변수:
+ *   - tx_data : I2C로 전송할 데이터 버퍼
+ *   - tx_len  : 전송할 데이터 길이 (바이트)
+ *   - id      : I2C 슬레이브 장치 주소
+ *
+ * 반환값: 없음 (void)
+ *
+ * 동작 방식:
+ *   1) I2C 명령 전송
+ *      - R_IICA0_Master_Send()로 지정한 슬레이브(id)에 tx_data 전송
+ *      - 전송 실패 시 UART로 "I2C Send Failed" 출력 후 함수 종료
+ *
+ *   2) UART 출력
+ *      - 전송 성공 시 "51" 문자열을 UART로 전송
+ *      - 디버깅 또는 전송 완료 신호용
+ *
+ * 참고:
+ *   - 읽기 기능 없이 명령 전송만 수행
+ *   - I2C 전원 제어나 초기화는 포함되어 있지 않음
+ */
+void I2C_Command_Mode_receiveData(const uint8_t *tx_data, uint8_t tx_len,uint8_t id )
+{
+    char uart_buf[16];
+    int j;
+    uint8_t rx[3] = {0};	
+    
+    if (R_IICA0_Master_Send((id << 1), tx_data, tx_len, 100) != MD_OK)
+    {
+        HOST_PRINT("I2C Send Failed\r\n");
+        return;
+    }
+
+    HOST_PRINT("51\r\n");
+}
+
+
+
+/**
+ * 함수명: I2C_Command_Mode_Send
+ * 목적: I2C 슬레이브 장치로부터 데이터를 읽고, UART로 출력
+ *
+ * 매개변수:
+ *   - tx_len : 읽을 데이터 길이 (바이트)
+ *   - id     : I2C 슬레이브 장치 주소
+ *
+ * 반환값: 없음 (void)
+ *
+ * 동작 방식:
+ *   1) I2C 데이터 수신
+ *      - R_IICA0_Master_Receive()를 사용하여 지정된 슬레이브(id)로부터 tx_len 바이트 읽기
+ *      - 실패 시 UART로 "I2C Receive Failed" 출력 후 함수 종료
+ *
+ *   2) UART 출력
+ *      - 첫 번째 바이트는 "%02X " 형식으로 바로 출력
+ *      - 그 다음 바이트들은 2바이트씩 묶어서 "%02X%02X " 형식으로 출력
+ *      - 마지막에 남은 1바이트는 단독으로 "%02X" 출력
+ *      - 모든 출력 후 줄바꿈("\r\n") 추가
+ *
+ *   3) delay
+ *      - 각 출력 사이에 delay를 넣어 UART 전송 안정화
+ *
+ * 참고:
+ *   - I2C 전원 제어나 초기화는 포함되어 있지 않음
+ *   - 출력 포맷은 디버깅 또는 로그용
+ */
+void I2C_Command_Mode_Send(uint8_t tx_len, uint8_t id)
+{
+    static uint8_t rx[600];
+    static char out[2*600 + 3];
+    uint16_t i;
+    uint16_t p = 0;
+    uint32_t guard = 0;
+
+    if (tx_len == 0) return;
+    if (tx_len > 600) tx_len = 600;
+
+    memset(rx, 0x00, sizeof(rx));
+
+    i2c_rx_done = 0;  // ✅ 수신 시작 전 클리어
+
+    if (R_IICA0_Master_Receive((id << 1), rx, tx_len, 1000) != MD_OK) {
+        HOST_PRINT("I2C Receive Failed\r\n");
+        return;
+    }
+
+    /* ✅ 수신 완료까지 대기 (delay로 때우지 말고 플래그로) */
+    while (!i2c_rx_done) {
+        if (guard++ > 3000000UL) {   // 타임아웃 (환경 맞게 조절)
+            HOST_PRINT("I2C RX Timeout\r\n");
+            return;
+        }
+    }
+
+    /* ✅ OWI처럼: 공백 없이 붙여서 출력 */
+    for (i = 0; i < tx_len; i++) {
+        uint8_t b = rx[i];
+        out[p++] = "0123456789ABCDEF"[b >> 4];
+        out[p++] = "0123456789ABCDEF"[b & 0x0F];
+    }
+    out[p++] = '\r';
+    out[p++] = '\n';
+    out[p] = '\0';
+
+    HOST_PRINT(out);
+}
+
+

i2c.h

@@ -0,0 +1,31 @@
+#include "r_cg_macrodriver.h"
+#include "r_cg_serial.h"
+#include "r_cg_port.h"
+#include "uart.h"
+
+#define SLAVE_ADDR 0x28
+
+#define RAM_BYTES 12
+extern volatile uint8_t i2c_tx_done;
+extern volatile uint8_t i2c_rx_done;
+
+
+void I2C_EnablePower(void);
+void I2C_DisablePower(void);
+void I2C_Command_Mode(void);
+//void I2C_read_nvm(void);
+void I2C_T_Command_Mode_receiveData(const uint8_t *tx_data, uint8_t tx_len,uint8_t id );
+void I2C_A_Command_Mode_receiveData(const uint8_t *tx_data, uint8_t tx_len,uint8_t id );
+void I2C_Command_Mode_receiveData(const uint8_t *tx_data, uint8_t tx_len,uint8_t id );
+void I2C_Command_Mode_Send(uint8_t tx_len, uint8_t id);
+
+
+void disable(void);
+
+void i2c_enter_nomal_mode(void);
+void i2c_read_ram_out0(void);
+void i2c_read_ram_out1(void);
+void i2c_read_all_ram(void);
+void i2c_read_all_nvm(void);
+void i2c_write_all_nvm(void);
+void i2c_nvm_data(void);

main.c

@@ -0,0 +1,35 @@
+/**********************************************************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+ * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+ * applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+ * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+ * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+ * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+ * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ *
+ * Copyright (C) 2020-2022 Renesas Electronics Corporation. All rights reserved.
+ *********************************************************************************************************************/
+/***********************************************************************/
+/*                                                                     */
+/*  FILE        :Main.c or Main.cpp                                    */
+/*  DATE        :                                                      */
+/*  DESCRIPTION :Main Program                                          */
+/*  CPU TYPE    :                                                      */
+/*                                                                     */
+/*  NOTE:THIS IS A TYPICAL EXAMPLE.                                    */
+/*                                                                     */
+/***********************************************************************/
+
+void main(void);
+
+void main(void)
+{
+
+}

owi.c

@@ -0,0 +1,588 @@
+#include "owi.h"
+#include "delay.h"
+#include "r_cg_wdt.h"
+#include <string.h>
+#include <stdio.h>
+#include "uart.h"
+#include "r_cg_wdt.h"
+
+#ifndef OWI_STRONG_DRIVE_HIGH_US
+#define OWI_STRONG_DRIVE_HIGH_US   5u
+#endif
+
+/* 내부 상태 */
+static uint32_t bit_period_us = OWI_BIT_PERIOD_US;
+static uint8_t  g_owi_timeout_latched = 0;
+
+static uint16_t g_owi_last_timeout_byte_index = 0xFFFFu;
+static uint8_t  g_owi_last_timeout_bit_index  = 0xFFu;
+
+static uint16_t g_owi_current_read_byte_index = 0u;
+static uint8_t  g_owi_current_read_bit_index  = 0u;
+
+/* =========================================================
+ * GPIO helpers (P70 / HW Open-Drain)
+ * - LOW  : 출력 모드 + 0
+ * - HIGH : 입력(Hi-Z)로 release
+ * ========================================================= */
+void GPIO_Clear(void)
+{
+    OWI_PORT_POM |= (uint8_t)OWI_PIN_MASK;
+    OWI_PORT_P   &= (uint8_t)~OWI_PIN_MASK;
+    OWI_PORT_PM  &= (uint8_t)~OWI_PIN_MASK;
+}
+
+void GPIO_Input(void)
+{
+    OWI_PORT_POM |= (uint8_t)OWI_PIN_MASK;
+    OWI_PORT_P   |= (uint8_t)OWI_PIN_MASK;
+    OWI_PORT_PM  |= (uint8_t)OWI_PIN_MASK;
+}
+
+int GPIO_Read(void)
+{
+    return (OWI_PORT_P & (uint8_t)OWI_PIN_MASK) ? 1 : 0;
+}
+
+static void OWI_Release(void)
+{
+    OWI_PORT_POM |= (uint8_t)OWI_PIN_MASK;
+    OWI_PORT_P   |= (uint8_t)OWI_PIN_MASK;
+    OWI_PORT_PM  |= (uint8_t)OWI_PIN_MASK;
+}
+
+static void GPIO_StrongDriveHighKick(uint32_t kick_us)
+{
+    OWI_Release();
+
+    if (!GPIO_Read()) {
+        return;
+    }
+
+    OWI_PORT_POM &= (uint8_t)~OWI_PIN_MASK;
+    OWI_PORT_P  |= (uint8_t)OWI_PIN_MASK;
+    OWI_PORT_PM &= (uint8_t)~OWI_PIN_MASK;
+
+    delay_us(kick_us);
+
+    OWI_PORT_POM |= (uint8_t)OWI_PIN_MASK;
+    OWI_Release();
+}
+
+void GPIO_ForceHighKick(void)
+{
+    GPIO_StrongDriveHighKick(OWI_STRONG_DRIVE_HIGH_US);
+}
+
+static void OWI_DriveLow(void)
+{
+    OWI_PORT_POM |= (uint8_t)OWI_PIN_MASK;
+    OWI_PORT_P   &= (uint8_t)~OWI_PIN_MASK;
+    OWI_PORT_PM  &= (uint8_t)~OWI_PIN_MASK;
+}
+
+/* =========================================================
+ * Diagnostics
+ * ========================================================= */
+uint8_t OWI_HasTimeout(void)
+{
+    return g_owi_timeout_latched;
+}
+
+void OWI_ClearTimeout(void)
+{
+    g_owi_timeout_latched = 0;
+    g_owi_last_timeout_byte_index = 0xFFFFu;
+    g_owi_last_timeout_bit_index  = 0xFFu;
+}
+
+uint16_t OWI_GetLastTimeoutByteIndex(void)
+{
+    return g_owi_last_timeout_byte_index;
+}
+
+uint8_t OWI_GetLastTimeoutBitIndex(void)
+{
+    return g_owi_last_timeout_bit_index;
+}
+
+/* =========================================================
+ * OWI Init
+ * ========================================================= */
+void OWI_Init(uint32_t bit_time_us)
+{
+    bit_period_us = bit_time_us;
+    (void)bit_period_us;
+
+    OWI_PORT_POM |= (uint8_t)OWI_PIN_MASK;
+    OWI_PORT_PU &= (uint8_t)~OWI_PIN_MASK;
+
+    OWI_ClearTimeout();
+    GPIO_Input();
+}
+
+/* =========================================================
+ * Start/Stop/Secure
+ * ========================================================= */
+void OWI_Start(void)
+{
+    GPIO_Clear();
+    delay_us(TSTART_HOLD);
+
+    GPIO_Input();
+    delay_us(TBIT);
+}
+
+void OWI_Stop(void)
+{
+    GPIO_Input();
+    delay_us(TSTOP_LOW);
+    delay_us(TIDLE);
+}
+
+static void OWI_StopWrite(void)
+{
+    OWI_Release();
+    delay_us(TSTOP_LOW);
+    delay_us(TIDLE);
+}
+
+static void OWI_StopRead(void)
+{
+    OWI_DriveLow();
+    delay_us(TSTOP_LOW);
+    OWI_Release();
+    delay_us(TIDLE);
+}
+
+static uint8_t OWI_WaitFirstBitStart(void)
+{
+    int timeout;
+
+    timeout = (int)(bit_period_us * 4u);
+
+    /* 첫 번째 HIGH->LOW 시작을 기다림 */
+    while (GPIO_Read() && timeout-- > 0) {
+        delay_us(1u);
+    }
+
+    if (timeout <= 0) {
+        if (!g_owi_timeout_latched) {
+            g_owi_timeout_latched = 1;
+            g_owi_last_timeout_byte_index = 0u;
+            g_owi_last_timeout_bit_index  = 0u;
+        }
+        return 0u;
+    }
+
+    return 1u;
+}
+
+static uint8_t OWI_WaitForFallingEdge(uint16_t byte_index, uint8_t bit_index)
+{
+    int timeout = (int)(bit_period_us * 4u);
+
+    while (GPIO_Read() && timeout-- > 0) {
+        delay_us(1u);
+    }
+
+    if (timeout <= 0) {
+        if (!g_owi_timeout_latched) {
+            g_owi_timeout_latched = 1;
+            g_owi_last_timeout_byte_index = byte_index;
+            g_owi_last_timeout_bit_index  = bit_index;
+        }
+        return 0u;
+    }
+
+    return 1u;
+}
+
+static uint8_t OWI_ReadByte_StreamSynced(uint16_t byte_index)
+{
+    uint8_t data = 0;
+    int b;
+
+    for (b = 7; b >= 0; b--) {
+        uint8_t bit_index = (uint8_t)(7 - b);
+        uint8_t bit;
+
+        g_owi_current_read_byte_index = byte_index;
+        g_owi_current_read_bit_index  = bit_index;
+
+        /* 슬롯 시작 후 중앙 샘플 */
+        delay_us(bit_period_us / 2u);
+        bit = GPIO_Read() ? 1u : 0u;
+        data |= (uint8_t)(bit << b);
+
+        /* 남은 반 슬롯 대기 */
+        delay_us(bit_period_us / 2u);
+    }
+
+    return data;
+}
+
+void OWI_SecureStop(void)
+{
+    int i;
+
+    GPIO_Clear();
+    delay_us(SECURE_HIGH);
+
+    for (i = 0; i < (int)SECURE_TOGGLE_COUNT; i++) {
+        GPIO_Input();
+        delay_us(SECURE_TOGGLE_HIGH);
+
+        GPIO_Clear();
+        delay_us(SECURE_TOGGLE_LOW);
+    }
+
+    GPIO_Input();
+    delay_us(SECURE_HIGH);
+
+    GPIO_Clear();
+    delay_us(TSTART_HOLD);
+    GPIO_Input();
+}
+
+/* =========================================================
+ * Bit/Byte IO
+ * ========================================================= */
+void OWI_WriteBit(int bit)
+{
+    uint32_t t_low  = bit ? (uint32_t)TLOW_1 : (uint32_t)TLOW_0;
+    uint32_t t_high = (uint32_t)TBIT - t_low;
+
+    /* HIGH 구간 */
+    OWI_Release();
+    delay_us(t_high);
+
+    /* LOW 구간 */
+    OWI_DriveLow();
+    delay_us(t_low);
+
+    /* 다음 슬롯 시작 전 반드시 release */
+    OWI_Release();
+}
+
+void OWI_WriteByte(uint8_t data)
+{
+    int i;
+    for (i = 7; i >= 0; i--) {
+        OWI_WriteBit((data >> i) & 0x01u);
+    }
+    GPIO_Input();
+}
+
+uint8_t OWI_ReadBit(void)
+{
+    int timeout;
+    int low_width = 0;
+
+    /* 1) 라인이 HIGH가 될 때까지 정리 */
+    timeout = (int)(bit_period_us * 2u);
+    while (!GPIO_Read() && timeout-- > 0) {
+        delay_us(1u);
+    }
+
+    if (timeout <= 0) {
+        if (!g_owi_timeout_latched) {
+            g_owi_timeout_latched = 1;
+            g_owi_last_timeout_byte_index = g_owi_current_read_byte_index;
+            g_owi_last_timeout_bit_index  = g_owi_current_read_bit_index;
+        }
+        return 0u;
+    }
+
+    /* 2) 다음 LOW 시작 대기 */
+    timeout = (int)(bit_period_us * 2u);
+    while (GPIO_Read() && timeout-- > 0) {
+        delay_us(1u);
+    }
+
+    if (timeout <= 0) {
+        if (!g_owi_timeout_latched) {
+            g_owi_timeout_latched = 1;
+            g_owi_last_timeout_byte_index = g_owi_current_read_byte_index;
+            g_owi_last_timeout_bit_index  = g_owi_current_read_bit_index;
+        }
+        return 0u;
+    }
+
+    /* 3) LOW가 유지되는 시간을 직접 측정 */
+    while (!GPIO_Read() && low_width < (int)(bit_period_us * 2u)) {
+        delay_us(1u);
+        low_width++;
+    }
+
+    /* 4) LOW 폭 기준으로 판정
+       - 짧으면 1
+       - 길면 0
+       threshold ~= TBIT/2
+    */
+    return (low_width < (int)(bit_period_us / 2u)) ? 1u : 0u;
+}
+
+uint8_t OWI_ReadByte(void)
+{
+    uint8_t data = 0;
+    int i;
+
+    for (i = 7; i >= 0; i--) {
+        g_owi_current_read_bit_index = (uint8_t)(7 - i);
+        data |= (uint8_t)(OWI_ReadBit() << i);
+        if (OWI_HasTimeout()) {
+            break;
+        }
+    }
+    return data;
+}
+
+/* =========================================================
+ * Debug Print
+ * ========================================================= */
+void OWI_T_ReadBytesAndPrint(int length)
+{
+    uint8_t buf[129];
+    int i;
+    char uart_buf[8];
+    char tmp_buf[8];
+    uint8_t va0, va1;
+
+    if (length > 129) length = 129;
+    if (length <= 0) return;
+
+    OWI_ClearTimeout();
+
+    for (i = 0; i < length; i++) {
+        R_WDT_Restart();
+        g_owi_current_read_byte_index = (uint16_t)i;
+        buf[i] = OWI_ReadByte();
+        if (OWI_HasTimeout()) {
+            i++;
+            break;
+        }
+    }
+
+    sprintf(uart_buf, "%02X ", buf[0]);
+    strcpy(tmp_buf, uart_buf);
+    HOST_PRINT(tmp_buf);
+
+    for (i = 1; i < length; i += 2) {
+        va0 = buf[i];
+        va1 = (uint8_t)((i + 1 < length) ? buf[i + 1] : 0u);
+
+        delay_us(200);
+        sprintf(uart_buf, "%02X%02X ", va0, va1);
+        strcpy(tmp_buf, uart_buf);
+        HOST_PRINT(tmp_buf);
+        delay_us(200);
+    }
+}
+
+/* =========================================================
+ * Raw helpers
+ * ========================================================= */
+static void owi_result_init(owi_io_result_t *r)
+{
+    if (!r) return;
+    memset(r, 0, sizeof(*r));
+    r->ok = 1;
+    r->timeout_byte_index = 0xFFFFu;
+    r->timeout_bit_index  = 0xFFu;
+}
+
+static void owi_result_latch_timeout(owi_io_result_t *r)
+{
+    if (!r) return;
+
+    if (OWI_HasTimeout()) {
+        r->ok = 0;
+        r->timeout = 1;
+        r->timeout_byte_index = OWI_GetLastTimeoutByteIndex();
+        r->timeout_bit_index  = OWI_GetLastTimeoutBitIndex();
+    }
+}
+
+void OWI_T_CommandModeRaw(const uint8_t *tx_data, uint8_t tx_len, uint8_t id, owi_io_result_t *r)
+{
+    int i;
+
+    owi_result_init(r);
+
+    //delay_us(200);
+    OWI_Init(OWI_BIT_PERIOD_US);
+    OWI_ClearTimeout();
+
+    R_WDT_Restart();
+    OWI_SecureStop();
+    R_WDT_Restart();
+    OWI_WriteByte((uint8_t)(id << 1));
+    R_WDT_Restart();
+
+    for (i = 0; i < (int)tx_len; i++) {
+        R_WDT_Restart();
+        OWI_WriteByte(tx_data[i]);
+        R_WDT_Restart();
+    }
+
+    OWI_Stop();
+    R_WDT_Restart();
+    owi_result_latch_timeout(r);
+}
+
+void OWI_CommandModeRaw(const uint8_t *tx_data, uint8_t tx_len, uint8_t id, owi_io_result_t *r)
+{
+    int i;
+
+    owi_result_init(r);
+    OWI_Init(OWI_BIT_PERIOD_US);
+    OWI_ClearTimeout();
+
+    R_WDT_Restart();
+    OWI_SecureStop();
+    R_WDT_Restart();
+    OWI_WriteByte((uint8_t)(id << 1));
+    R_WDT_Restart();
+
+    for (i = 0; i < (int)tx_len; i++) {
+        R_WDT_Restart();
+        OWI_WriteByte(tx_data[i]);
+        R_WDT_Restart();
+    }
+
+    OWI_Stop();
+    R_WDT_Restart();
+    owi_result_latch_timeout(r);
+}
+
+void OWI_ReadBytesRaw(int length, uint8_t id, owi_io_result_t *r)
+{
+    int i;
+    int max_len;
+    uint8_t is_long_read;
+
+    if (!r) return;
+
+    owi_result_init(r);
+    OWI_Init(OWI_BIT_PERIOD_US);
+
+    if (length <= 0) {
+        r->ok = 0;
+        return;
+    }
+
+    max_len = (int)OWI_IO_MAX_BYTES;
+    if (length > max_len) {
+        length = max_len;
+    }
+
+    r->read_len = (uint16_t)length;
+    OWI_ClearTimeout();
+
+    /* Only 119 keeps the established mid-stream sync. */
+    is_long_read = (length == 119) ? 1u : 0u;
+
+    R_WDT_Restart();
+    OWI_SecureStop();
+    OWI_WriteByte((uint8_t)((id << 1) | 1u));
+
+    /*
+     * For 129 bytes, wait for the first edge immediately after the read ID.
+     * The old 100us delay could enter an already-started first pulse.
+     * Preserve the established delay for every other read length.
+     */
+    if (length != 129) {
+        delay_us(100u);
+    }
+
+    R_WDT_Restart();
+    if (!OWI_WaitForFallingEdge(0u, 0u)) {
+        owi_result_latch_timeout(r);
+        OWI_StopRead();
+        return;
+    }
+
+    for (i = 0; i < length; i++) {
+        R_WDT_Restart();
+
+        /* Preserve the existing mid-stream sync for the 119-byte path only. */
+        if (is_long_read && i == (length - 50)) {
+            R_WDT_Restart();
+            if (!OWI_WaitForFallingEdge((uint16_t)i, 0u)) {
+                owi_result_latch_timeout(r);
+                break;
+            }
+        }
+
+        r->data[i] = OWI_ReadByte_StreamSynced((uint16_t)i);
+
+        if (OWI_HasTimeout()) {
+            owi_result_latch_timeout(r);
+            break;
+        }
+    }
+
+    OWI_StopRead();
+}
+
+void OWI_disable(void)
+{
+    HOST_PRINT("51\r\n");
+}
+
+void OWI_T_CommandMode(const uint8_t *tx_data, uint8_t tx_len, uint8_t id)
+{
+    owi_io_result_t r;
+    (void)r;
+
+    OWI_T_CommandModeRaw(tx_data, tx_len, id, &r);
+    HOST_PRINT("51\r\n");
+}
+
+void OWI_CommandMode(const uint8_t *tx_data, uint8_t tx_len, uint8_t id)
+{
+    owi_io_result_t r;
+    (void)r;
+
+    OWI_CommandModeRaw(tx_data, tx_len, id, &r);
+    HOST_PRINT("51\r\n");
+}
+
+void OWI_ReadBytesAndPrint(int length, uint8_t id)
+{
+    owi_io_result_t r;
+    char out[(2 * OWI_IO_MAX_BYTES) + 40];
+    int i;
+    uint16_t p = 0;
+
+    if (length <= 0) {
+        HOST_PRINT("Err:read_len_nonzero\r\n");
+        return;
+    }
+
+    OWI_ReadBytesRaw(length, id, &r);
+
+    if (r.read_len == 0) {
+        HOST_PRINT("Err:read_len_nonzero\r\n");
+        return;
+    }
+
+    for (i = 0; i < (int)r.read_len; i++) {
+        uint8_t b = r.data[i];
+        out[p++] = "0123456789ABCDEF"[b >> 4];
+        out[p++] = "0123456789ABCDEF"[b & 0x0F];
+    }
+
+    if (r.timeout) {
+        p += (uint16_t)sprintf(&out[p], " !TO(B%u b%u)",
+                               (unsigned)r.timeout_byte_index,
+                               (unsigned)r.timeout_bit_index);
+    }
+
+    out[p++] = '\r';
+    out[p++] = '\n';
+    out[p] = '\0';
+
+    HOST_PRINT(out);
+}

owi.h

@@ -0,0 +1,76 @@
+#ifndef OWI_H
+#define OWI_H
+
+#include "r_cg_macrodriver.h"
+#include "r_cg_serial.h"
+#include "r_cg_port.h"
+#include <stdint.h>
+
+#define OWI_PORT_P     P7
+#define OWI_PORT_PM    PM7
+#define OWI_PORT_PU    PU7
+#define OWI_PORT_POM   POM7
+#define OWI_PIN_MASK   (1u << 0)
+
+/* 먼저 1200us로 고정해서 테스트 */
+#define OWI_BIT_PERIOD_US     1200u
+#define TBIT                  OWI_BIT_PERIOD_US
+#define TLOW_0                ((TBIT * 3u) / 4u)
+#define TLOW_1                ((TBIT * 1u) / 4u)
+#define TSTOP_LOW             (TBIT * 2u)
+#define TIDLE                 (TBIT * 3u)
+#define TSTART_HOLD           50u
+#define SECURE_HIGH           (2u * TBIT)
+#define SECURE_TOGGLE_COUNT   3u
+#define SECURE_TOGGLE_LOW     (TBIT / 4u)
+#define SECURE_TOGGLE_HIGH    (TBIT / 5u)
+
+#ifndef RAM_BYTES
+#define RAM_BYTES 3
+#endif
+
+#define OWI_IO_MAX_BYTES 320u
+
+typedef struct {
+    uint8_t  ok;
+    uint8_t  timeout;
+    uint16_t read_len;
+    uint8_t  data[OWI_IO_MAX_BYTES];
+    uint16_t timeout_byte_index;
+    uint8_t  timeout_bit_index;
+} owi_io_result_t;
+
+void GPIO_Clear(void);
+void GPIO_Input(void);
+int  GPIO_Read(void);
+
+void OWI_Init(uint32_t bit_time_us);
+void OWI_Start(void);
+void OWI_Stop(void);
+void OWI_SecureStop(void);
+
+void    OWI_WriteBit(int bit);
+void    OWI_WriteByte(uint8_t data);
+uint8_t OWI_ReadBit(void);
+uint8_t OWI_ReadByte(void);
+
+void OWI_T_ReadBytesAndPrint(int length);
+void OWI_ReadBytesAndPrint(int length, uint8_t id);
+
+void OWI_T_CommandMode(const uint8_t *tx_data, uint8_t tx_len, uint8_t id);
+void OWI_CommandMode  (const uint8_t *tx_data, uint8_t tx_len, uint8_t id);
+void OWI_A_CommandMode(const uint8_t *tx_data, uint8_t tx_len, uint8_t id);
+
+void OWI_T_CommandModeRaw(const uint8_t *tx_data, uint8_t tx_len, uint8_t id, owi_io_result_t *r);
+void OWI_CommandModeRaw  (const uint8_t *tx_data, uint8_t tx_len, uint8_t id, owi_io_result_t *r);
+void OWI_ReadBytesRaw    (int length, uint8_t id, owi_io_result_t *r);
+
+void OWI_disable(void);
+void GPIO_ForceHighKick(void);
+
+uint8_t  OWI_HasTimeout(void);
+void     OWI_ClearTimeout(void);
+uint16_t OWI_GetLastTimeoutByteIndex(void);
+uint8_t  OWI_GetLastTimeoutBitIndex(void);
+
+#endif

r_cg_adc.c

@@ -0,0 +1,161 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_adc.c
+* Version      : CodeGenerator for RL78/F14 V2.03.07.02 [08 Nov 2021]
+* Device(s)    : R5F10PPJ
+* Tool-Chain   : CCRL
+* Description  : This file implements device driver for ADC module.
+* Creation Date: 2026-01-13
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "r_cg_adc.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+* Function Name: R_ADC_Create
+* Description  : This function initializes the AD converter.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_ADC_Create(void)
+{
+    ADCEN = 1U;  /* supply AD clock */
+    ADM0 = _00_AD_ADM0_INITIALVALUE;  /* disable AD conversion and clear ADM0 register */
+    ADMK = 1U;  /* disable INTAD interrupt */
+    ADIF = 0U;  /* clear INTAD interrupt flag */
+    /* Set INTAD low priority */
+    ADPR1 = 1U;
+    ADPR0 = 1U;
+    /* The reset status of ADPC is analog input, so it's unnecessary to set. */
+    /* Set ANI0 - ANI23 pin as analog input */
+    PM10 |= 0x3FU;
+    PM9 |= 0xFFU;
+    PM8 |= 0xFFU;
+    PM3 |= 0x18U;
+    /* Set ANI24 pin */
+    PMC12 |= 0x20U;
+    PM12 |= 0x20U;
+    /* Set ANI25 pin */
+    PMC12 |= 0x01U;
+    PM12 |= 0x01U;
+    /* Set ANI26 pin */
+    PMC7 |= 0x01U;
+    PM7 |= 0x01U;
+    /* Set ANI27 pin */
+    PMC7 |= 0x02U;
+    PM7 |= 0x02U;
+    /* Set ANI28 pin */
+    PMC7 |= 0x04U;
+    PM7 |= 0x04U;
+    /* Set ANI29 pin */
+    PMC7 |= 0x08U;
+    PM7 |= 0x08U;
+    /* Set ANI30 pin */
+    PMC7 |= 0x10U;
+    PM7 |= 0x10U;
+    ADM0 = _00_AD_CONVERSION_CLOCK_64 | _00_AD_TIME_MODE_NORMAL_1 | _00_AD_OPERMODE_SELECT;
+    ADM1 = _00_AD_TRIGGER_SOFTWARE | _00_AD_CONVMODE_CONSELECT;
+    ADM2 = _00_AD_POSITIVE_VDD | _00_AD_NEGATIVE_VSS | _00_AD_AREA_MODE_1 | _00_AD_RESOLUTION_10BIT;
+    ADUL = _FF_AD_ADUL_VALUE;
+    ADLL = _00_AD_ADLL_VALUE;
+    ADS = _00_AD_INPUT_CHANNEL_0;
+}
+
+/***********************************************************************************************************************
+* Function Name: R_ADC_Start
+* Description  : This function starts the AD converter.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_ADC_Start(void)
+{
+    ADIF = 0U;  /* clear INTAD interrupt flag */
+    ADMK = 0U;  /* enable INTAD interrupt */
+    ADCS = 1U;  /* enable AD conversion */
+}
+
+/***********************************************************************************************************************
+* Function Name: R_ADC_Stop
+* Description  : This function stops the AD converter.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_ADC_Stop(void)
+{
+    ADCS = 0U;  /* disable AD conversion */
+    ADMK = 1U;  /* disable INTAD interrupt */
+    ADIF = 0U;  /* clear INTAD interrupt flag */
+}
+
+/***********************************************************************************************************************
+* Function Name: R_ADC_Set_OperationOn
+* Description  : This function enables comparator operation.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_ADC_Set_OperationOn(void)
+{
+    ADCE = 1U;  /* enable AD comparator */
+}
+
+/***********************************************************************************************************************
+* Function Name: R_ADC_Set_OperationOff
+* Description  : This function stops comparator operation.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_ADC_Set_OperationOff(void)
+{
+    ADCE = 0U;  /* disable AD comparator */
+}
+
+/***********************************************************************************************************************
+* Function Name: R_ADC_Get_Result
+* Description  : This function returns the conversion result in the buffer.
+* Arguments    : buffer -
+*                    the address where to write the conversion result
+* Return Value : None
+***********************************************************************************************************************/
+void R_ADC_Get_Result(uint16_t * const buffer)
+{
+    *buffer = (uint16_t)(ADCR >> 6U);
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */

r_cg_adc.h

@@ -0,0 +1,223 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_adc.h
+* Version      : CodeGenerator for RL78/F14 V2.03.07.02 [08 Nov 2021]
+* Device(s)    : R5F10PPJ
+* Tool-Chain   : CCRL
+* Description  : This file implements device driver for ADC module.
+* Creation Date: 2026-01-13
+***********************************************************************************************************************/
+
+#ifndef ADC_H
+#define ADC_H
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+/*
+    Peripheral enable register 0 (PER0)
+*/
+/* Control of AD converter input clock (ADCEN) */
+#define _00_AD_CLOCK_STOP               (0x00U) /* stop supply of input clock */
+#define _20_AD_CLOCK_SUPPLY             (0x20U) /* supply input clock */
+
+/*
+    AD converter mode register 0 (ADM0)
+*/
+#define _00_AD_ADM0_INITIALVALUE        (0x00U)
+/* AD conversion operation control (ADCS) */
+#define _80_AD_CONVERSION_ENABLE        (0x80U) /* enable AD conversion operation control */
+#define _00_AD_CONVERSION_DISABLE       (0x00U) /* disable AD conversion operation control */
+/* Specification of AD conversion operation mode (ADMD) */
+#define _00_AD_OPERMODE_SELECT          (0x00U) /* select operation mode */
+#define _40_AD_OPERMODE_SCAN            (0x40U) /* scan operation mode */
+/* AD conversion clock selection (FR2 - FR0) */
+#define _00_AD_CONVERSION_CLOCK_64      (0x00U) /* fCLK/64 */
+#define _08_AD_CONVERSION_CLOCK_32      (0x08U) /* fCLK/32 */
+#define _10_AD_CONVERSION_CLOCK_16      (0x10U) /* fCLK/16 */
+#define _18_AD_CONVERSION_CLOCK_8       (0x18U) /* fCLK/8 */
+#define _20_AD_CONVERSION_CLOCK_6       (0x20U) /* fCLK/6 */
+#define _28_AD_CONVERSION_CLOCK_5       (0x28U) /* fCLK/5 */
+#define _30_AD_CONVERSION_CLOCK_4       (0x30U) /* fCLK/4 */
+#define _38_AD_CONVERSION_CLOCK_2       (0x38U) /* fCLK/2 */
+/* Specification AD conversion time mode (LV1, LV0) */
+#define _00_AD_TIME_MODE_NORMAL_1       (0x00U) /* normal 1 mode */
+#define _02_AD_TIME_MODE_NORMAL_2       (0x02U) /* normal 2 mode */
+/* AD comparator operation control (ADCE) */
+#define _01_AD_COMPARATOR_ENABLE        (0x01U) /* enable comparator operation control */
+#define _00_AD_COMPARATOR_DISABLE       (0x00U) /* disable comparator operation control */
+
+/*
+    Analog input channel specification register (ADS)
+*/
+/* Specification of analog input channel (ADISS, ADS4 - ADS0) */
+/* Select mode */
+#define _00_AD_INPUT_CHANNEL_0          (0x00U) /* ANI0 */
+#define _01_AD_INPUT_CHANNEL_1          (0x01U) /* ANI1 */
+#define _02_AD_INPUT_CHANNEL_2          (0x02U) /* ANI2 */
+#define _03_AD_INPUT_CHANNEL_3          (0x03U) /* ANI3 */
+#define _04_AD_INPUT_CHANNEL_4          (0x04U) /* ANI4 */
+#define _05_AD_INPUT_CHANNEL_5          (0x05U) /* ANI5 */
+#define _06_AD_INPUT_CHANNEL_6          (0x06U) /* ANI6 */
+#define _07_AD_INPUT_CHANNEL_7          (0x07U) /* ANI7 */
+#define _08_AD_INPUT_CHANNEL_8          (0x08U) /* ANI8 */
+#define _09_AD_INPUT_CHANNEL_9          (0x09U) /* ANI9 */
+#define _0A_AD_INPUT_CHANNEL_10         (0x0AU) /* ANI10 */
+#define _0B_AD_INPUT_CHANNEL_11         (0x0BU) /* ANI11 */
+#define _0C_AD_INPUT_CHANNEL_12         (0x0CU) /* ANI12 */
+#define _0D_AD_INPUT_CHANNEL_13         (0x0DU) /* ANI13 */
+#define _0E_AD_INPUT_CHANNEL_14         (0x0EU) /* ANI14 */
+#define _0F_AD_INPUT_CHANNEL_15         (0x0FU) /* ANI15 */
+#define _10_AD_INPUT_CHANNEL_16         (0x10U) /* ANI16 */
+#define _11_AD_INPUT_CHANNEL_17         (0x11U) /* ANI17 */
+#define _12_AD_INPUT_CHANNEL_18         (0x12U) /* ANI18 */
+#define _13_AD_INPUT_CHANNEL_19         (0x13U) /* ANI19 */
+#define _14_AD_INPUT_CHANNEL_20         (0x14U) /* ANI20 */
+#define _15_AD_INPUT_CHANNEL_21         (0x15U) /* ANI21 */
+#define _16_AD_INPUT_CHANNEL_22         (0x16U) /* ANI22 */
+#define _17_AD_INPUT_CHANNEL_23         (0x17U) /* ANI23 */
+#define _18_AD_INPUT_CHANNEL_24         (0x18U) /* ANI24 */
+#define _19_AD_INPUT_CHANNEL_25         (0x19U) /* ANI25 */
+#define _1A_AD_INPUT_CHANNEL_26         (0x1AU) /* ANI26 */
+#define _1B_AD_INPUT_CHANNEL_27         (0x1BU) /* ANI27 */
+#define _1C_AD_INPUT_CHANNEL_28         (0x1CU) /* ANI28 */
+#define _1D_AD_INPUT_CHANNEL_29         (0x1DU) /* ANI29 */
+#define _1E_AD_INPUT_CHANNEL_30         (0x1EU) /* ANI30 */
+#define _80_AD_INPUT_TEMPERSENSOR_0     (0x80U) /* temperature sensor 0 output is used to be the input channel */
+#define _81_AD_INPUT_INTERREFVOLT       (0x81U) /* internal reference voltage output is used to be the input channel */
+/* Scan mode */
+#define _00_AD_INPUT_CHANNEL_0_3        (0x00U) /* ANI0 - ANI3 */
+#define _01_AD_INPUT_CHANNEL_1_4        (0x01U) /* ANI1 - ANI4 */
+#define _02_AD_INPUT_CHANNEL_2_5        (0x02U) /* ANI2 - ANI5 */
+#define _03_AD_INPUT_CHANNEL_3_6        (0x03U) /* ANI3 - ANI6 */
+#define _04_AD_INPUT_CHANNEL_4_7        (0x04U) /* ANI4 - ANI7 */
+#define _05_AD_INPUT_CHANNEL_5_8        (0x05U) /* ANI5 - ANI8 */
+#define _06_AD_INPUT_CHANNEL_6_9        (0x06U) /* ANI6 - ANI9 */
+#define _07_AD_INPUT_CHANNEL_7_10       (0x07U) /* ANI7 - ANI10 */
+#define _08_AD_INPUT_CHANNEL_8_11       (0x08U) /* ANI8 - ANI11 */
+#define _09_AD_INPUT_CHANNEL_9_12       (0x09U) /* ANI9 - ANI12 */
+#define _0A_AD_INPUT_CHANNEL_10_13      (0x0AU) /* ANI10 - ANI13 */
+#define _0B_AD_INPUT_CHANNEL_11_14      (0x0BU) /* ANI11 - ANI14 */
+#define _0C_AD_INPUT_CHANNEL_12_15      (0x0CU) /* ANI12 - ANI15 */
+#define _0D_AD_INPUT_CHANNEL_13_16      (0x0DU) /* ANI13 - ANI16 */
+#define _0E_AD_INPUT_CHANNEL_14_17      (0x0EU) /* ANI14 - ANI17 */
+#define _0F_AD_INPUT_CHANNEL_15_18      (0x0FU) /* ANI15 - ANI18 */
+#define _10_AD_INPUT_CHANNEL_16_19      (0x10U) /* ANI16 - ANI19 */
+#define _11_AD_INPUT_CHANNEL_17_20      (0x11U) /* ANI17 - ANI20 */
+#define _12_AD_INPUT_CHANNEL_18_21      (0x12U) /* ANI18 - ANI21 */
+#define _13_AD_INPUT_CHANNEL_19_22      (0x13U) /* ANI19 - ANI22 */
+#define _14_AD_INPUT_CHANNEL_20_23      (0x14U) /* ANI20 - ANI23 */
+
+/*
+    AD converter mode register 1 (ADM1)
+*/
+/* AD trigger mode selection (ADTMD1, ADTMD0) */
+#define _00_AD_TRIGGER_SOFTWARE         (0x00U) /* software trigger mode */
+#define _80_AD_TRIGGER_HARDWARE_NOWAIT  (0x80U) /* hardware trigger mode (no wait) */
+#define _C0_AD_TRIGGER_HARDWARE_WAIT    (0xC0U) /* hardware trigger mode (wait) */
+/* AD convertion mode selection (ADSCM) */
+#define _00_AD_CONVMODE_CONSELECT       (0x00U) /* continuous convertion mode */
+#define _20_AD_CONVMODE_ONESELECT       (0x20U) /* oneshot convertion mode */
+/* Trigger signal selection (ADTRS1, ADTRS0) */
+#define _00_AD_TRIGGER_INTTM01          (0x00U) /* INTTM01 */
+#define _01_AD_TRIGGER_ELC              (0x01U) /* ELC */
+#define _01_AD_TRIGGER_TIMER            (0x01U) /* INTTRD0,INTTRJ0 */
+#define _02_AD_TRIGGER_INTRTC           (0x02U) /* INTRTC */
+/*
+    AD converter mode register 2 (ADM2)
+*/
+/* AD VREF(+) selection (ADREFP1, ADREFP0) */
+#define _00_AD_POSITIVE_VDD             (0x00U) /* use VDD as VREF(+) */
+#define _40_AD_POSITIVE_AVREFP          (0x40U) /* use AVREFP as VREF(+) */
+#define _80_AD_POSITIVE_INTERVOLT       (0x80U) /* use internal voltage as VREF(+) */
+/* AD VREF(-) selection (ADREFM) */
+#define _00_AD_NEGATIVE_VSS             (0x00U) /* use VSS as VREF(-) */
+#define _20_AD_NEGATIVE_AVREFM          (0x20U) /* use AVREFM as VREF(-) */
+/* AD conversion result upper/lower bound value selection (ADRCK) */
+#define _00_AD_AREA_MODE_1              (0x00U) /* generates INTAD when ADLL <= ADCRH <= ADUL */
+#define _08_AD_AREA_MODE_2_3            (0x08U) /* generates INTAD when ADUL < ADCRH or ADLL > ADCRH */
+/* AD wakeup function selection (AWC) */
+#define _00_AD_WAKEUP_OFF               (0x00U) /* stop wakeup function */
+#define _04_AD_WAKEUP_ON                (0x04U) /* use wakeup function */
+/* AD resolution selection (ADTYP) */
+#define _00_AD_RESOLUTION_10BIT         (0x00U) /* 10 bits */
+#define _01_AD_RESOLUTION_8BIT          (0x01U) /* 8 bits */
+
+/*
+    AD test function register (ADTES)
+*/
+/* AD test mode signal (ADTES2 - ADTES0) */
+#define _00_AD_NORMAL_INPUT             (0x00U) /* normal mode */
+#define _02_AD_TEST_AVREFM              (0x02U) /* use AVREFM as test signal */
+#define _03_AD_TEST_AVREFP              (0x03U) /* use AVREFP as test signal */
+/*
+    Format of A/D Converter Trigger Select Register 0 (ADTRGS0)(F13 only)
+*/
+/* Selection of the operation trigger of the A/D converter when the timer RD0 input capture B/compare match B
+interrupt request is generated (ADTRGS00) */
+#define _01_AD_TRIGGER_INTTRD0          (0x01U) /* A/D conversion is started when the interrupt request is generated */
+
+/*
+    Format of A/D Converter Trigger Select Register 1 (ADTRGS1)(F13 only)
+*/
+/* Selection of the operation trigger of the A/D converter when the timer RJ0 interrupt request is generated (ADTRGS10) */
+#define _01_AD_TRIGGER_INTTRJ0          (0x01U) /* A/D conversion is started when the interrupt request is generated */
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+/* Upper bound (ADUL) value */
+#define _FF_AD_ADUL_VALUE               (0xFFU)
+/* Upper bound (ADLL) value */
+#define _00_AD_ADLL_VALUE               (0x00U)
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+typedef enum
+{
+    ADCHANNEL0, ADCHANNEL1, ADCHANNEL2, ADCHANNEL3, ADCHANNEL4, ADCHANNEL5, ADCHANNEL6,
+    ADCHANNEL7, ADCHANNEL8, ADCHANNEL9, ADCHANNEL10, ADCHANNEL11, ADCHANNEL12,
+    ADCHANNEL13, ADCHANNEL14, ADCHANNEL15, ADCHANNEL16, ADCHANNEL17, ADCHANNEL18, 
+    ADCHANNEL19, ADCHANNEL20, ADCHANNEL21, ADCHANNEL22, ADCHANNEL23, ADCHANNEL24 = 24U,
+    ADCHANNEL25, ADCHANNEL26, ADCHANNEL27, ADCHANNEL28, ADCHANNEL29, ADCHANNEL30,
+    ADTEMPERSENSOR0 = 128U, ADINTERREFVOLT
+} ad_channel_t;
+typedef enum
+{
+    ADNORMALINPUT,
+    ADAVREFM = 2U,
+    ADAVREFP
+} test_channel_t;
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+void R_ADC_Create(void);
+void R_ADC_Start(void);
+void R_ADC_Stop(void);
+void R_ADC_Set_OperationOn(void);
+void R_ADC_Set_OperationOff(void);
+void R_ADC_Get_Result(uint16_t * const buffer);
+
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif

r_cg_adc_user.c

@@ -0,0 +1,64 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_adc_user.c
+* Version      : CodeGenerator for RL78/F14 V2.03.07.02 [08 Nov 2021]
+* Device(s)    : R5F10PPJ
+* Tool-Chain   : CCRL
+* Description  : This file implements device driver for ADC module.
+* Creation Date: 2026-01-13
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "r_cg_adc.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+#pragma interrupt r_adc_interrupt(vect=INTAD)
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+* Function Name: r_adc_interrupt
+* Description  : This function is INTAD interrupt service routine.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+static void __near r_adc_interrupt(void)
+{
+    /* Start user code. Do not edit comment generated here */
+    /* End user code. Do not edit comment generated here */
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */

r_cg_cgc.c

@@ -0,0 +1,82 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_cgc.c
+* Version      : CodeGenerator for RL78/F14 V2.03.07.02 [08 Nov 2021]
+* Device(s)    : R5F10PPJ
+* Tool-Chain   : CCRL
+* Description  : This file implements device driver for CGC module.
+* Creation Date: 2026-08-03
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "r_cg_cgc.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+* Function Name: R_CGC_Create
+* Description  : This function initializes the clock generator.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_CGC_Create(void)
+{
+    /* Set fSL */
+    SELLOSC = 1U;
+    /* Set fMX */
+    CMC = _00_CGC_HISYS_PORT | _00_CGC_SUB_PORT | _00_CGC_SYSOSC_DEFAULT | _00_CGC_SUBMODE_DEFAULT;
+    MSTOP = 1U;
+    /* Set fMAIN */
+    MCM0 = 0U;
+    MDIV = _01_CGC_FMP_DIV_1;
+    /* Set fMP to clock through mode */
+    SELPLL = 0U;
+    /* Set fSUB */
+    XTSTOP = 1U;
+    /* Set fCLK */
+    CSS = 0U;
+    /* Set fIH */
+    HIOSTOP = 0U;
+    /* Set RTC clock source */
+    RTCCL = _80_CGC_RTC_FIH;
+    RTCCL |= _42_CGC_RTC_DIV122;
+    /* Set Timer RD clock source to fCLK, fMP */
+    TRD_CKSEL = 0U;
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */

r_cg_cgc.h

@@ -0,0 +1,227 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_cgc.h
+* Version      : CodeGenerator for RL78/F14 V2.03.07.02 [08 Nov 2021]
+* Device(s)    : R5F10PPJ
+* Tool-Chain   : CCRL
+* Description  : This file implements device driver for CGC module.
+* Creation Date: 2026-08-03
+***********************************************************************************************************************/
+
+#ifndef CGC_H
+#define CGC_H
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+/*
+    Clock operation mode control register (CMC)
+*/
+/* High-speed system clock pin operation mode (EXCLK, OSCSEL) */
+#define _C0_CGC_HISYS_PIN           (0xC0U)
+#define _00_CGC_HISYS_PORT          (0x00U) /* X1, X2 as I/O port */
+#define _40_CGC_HISYS_OSC           (0x40U) /* X1, X2 as crystal/ceramic resonator connection */
+#define _80_CGC_HISYS_PORT1         (0x80U) /* X1, X2 as I/O port */
+#define _C0_CGC_HISYS_EXT           (0xC0U) /* X1 as I/O port, X2 as external clock input */
+/* Subsystem clock pin operation mode (EXCLKS, OSCSELS) */
+#define _30_CGC_SUB_PIN             (0x30U)
+#define _00_CGC_SUB_PORT            (0x00U) /* XT1, XT2 as I/O port */
+#define _10_CGC_SUB_OSC             (0x10U) /* XT1, XT2 as crystal connection */
+#define _20_CGC_SUB_PORT1           (0x20U) /* XT1, XT2 as I/O port */
+#define _30_CGC_SUB_EXT             (0x30U) /* XT1 as I/O port, XT2 as external clock input */
+/* XT1 oscillator oscillation mode selection (AMPHS1, AMPHS0) */
+#define _00_CGC_SUBMODE_DEFAULT     (0x00U)
+#define _00_CGC_SUBMODE_LOW         (0x00U) /* low power consumption oscillation */
+#define _02_CGC_SUBMODE_NORMAL      (0x02U) /* normal oscillation */
+#define _04_CGC_SUBMODE_ULOW        (0x04U) /* ultra-low power consumption oscillation */
+/* Control of X1 high-speed system clock oscillation frequency (AMPH) */
+#define _00_CGC_SYSOSC_DEFAULT      (0x00U)
+#define _00_CGC_SYSOSC_UNDER10M     (0x00U) /* fX <= 10MHz */
+#define _01_CGC_SYSOSC_OVER10M      (0x01U) /* fX > 10MHz */
+
+/*
+    Clock operation status control register (CSC)
+*/
+/* Control of high-speed system clock operation (MSTOP) */
+#define _00_CGC_HISYS_OPER          (0x00U) /* X1 oscillator/external clock operating */
+#define _80_CGC_HISYS_STOP          (0x80U) /* X1 oscillator/external clock stopped */
+/* Subsystem clock operation (XTSTOP) */
+#define _00_CGC_SUB_OPER            (0x00U) /* XT1 oscillator operating */
+#define _40_CGC_SUB_STOP            (0x40U) /* XT1 oscillator stopped */
+/* High-speed OCO operation (HIOSTOP) */
+#define _00_CGC_HIO_OPER            (0x00U) /* high-speed OCO operating */
+#define _01_CGC_HIO_STOP            (0x01U) /* high-speed OCO stopped */
+
+/*
+    Oscillation stabilization time counter status register (OSTC)
+*/
+/* Oscillation stabilization time status (MOST18 - MOST8) */
+#define _00_CGC_OSCSTAB_STA0        (0x00U) /* < 2^8/fX */
+#define _80_CGC_OSCSTAB_STA8        (0x80U) /* 2^8/fX */
+#define _C0_CGC_OSCSTAB_STA9        (0xC0U) /* 2^9/fX */
+#define _E0_CGC_OSCSTAB_STA10       (0xE0U) /* 2^10/fX */
+#define _F0_CGC_OSCSTAB_STA11       (0xF0U) /* 2^11/fX */
+#define _F8_CGC_OSCSTAB_STA13       (0xF8U) /* 2^13/fX */
+#define _FC_CGC_OSCSTAB_STA15       (0xFCU) /* 2^15/fX */
+#define _FE_CGC_OSCSTAB_STA17       (0xFEU) /* 2^17/fX */
+#define _FF_CGC_OSCSTAB_STA18       (0xFFU) /* 2^18/fX */
+
+/*
+    Oscillation stabilization time select register (OSTS)
+*/
+/* Oscillation stabilization time selection (OSTS2 - OSTS0) */
+#define _00_CGC_OSCSTAB_SEL8        (0x00U) /* 2^8/fX */
+#define _01_CGC_OSCSTAB_SEL9        (0x01U) /* 2^9/fX */
+#define _02_CGC_OSCSTAB_SEL10       (0x02U) /* 2^10/fX */
+#define _03_CGC_OSCSTAB_SEL11       (0x03U) /* 2^11/fX */
+#define _04_CGC_OSCSTAB_SEL13       (0x04U) /* 2^13/fX */
+#define _05_CGC_OSCSTAB_SEL15       (0x05U) /* 2^15/fX */
+#define _06_CGC_OSCSTAB_SEL17       (0x06U) /* 2^17/fX */
+#define _07_CGC_OSCSTAB_SEL18       (0x07U) /* 2^18/fX */
+
+/*
+    PLL control register (PLLCTL)
+*/
+/* Lockup wait counter setting value */
+#define _00_CGC_LOCKUP_WAIT_7       (0x00U) /* 2^7/fMAIN */
+#define _40_CGC_LOCKUP_WAIT_8       (0x40U) /* 2^8/fMAIN */
+#define _80_CGC_LOCKUP_WAIT_9       (0x80U) /* 2^9/fMAIN */
+/* PLL output clock selection (PLLDIV1) */
+#define _00_CGC_PLL_BELOW_32MHZ     (0x00U) /* when fMAIN <= 32 MHz */
+#define _20_CGC_PLL_ABOVE_32MHZ     (0x20U) /* when fMAIN > 32 MHz */
+/* PLL output clock division selection (PLLDIV0) */
+#define _00_CGC_PLL_DIVISION_2      (0x00U) /* divides the clock frequency by 2 */
+#define _10_CGC_PLL_DIVISION_4      (0x10U) /* divides the clock frequency by 4 */
+/* Clock mode selection (SELPLL) */
+#define _00_CGC_NOSEL_PLL           (0x00U) /* clock through mode */
+#define _04_CGC_SEL_PLL             (0x04U) /* PLL clock select mode */
+/* PLL output clock (fPLLO) multiplier selection (PLLMUL) */
+#define _00_CGC_PLL_MULTIPLY_X12    (0x00U) /* clock through mode */
+#define _02_CGC_PLL_MULTIPLY_X16    (0x02U) /* PLL clock select mode */
+/* Operating or stopping PLL function (PLLON) */
+#define _00_CGC_PLL_STOP            (0x00U) /* PLL operating stopped */
+#define _01_CGC_PLL_ENABLE          (0x01U) /* PLL operating */
+
+/*
+    PLL status register (PLLSTS)
+*/
+/* PLL lock state */
+#define _00_CGC_PLL_UNLOCKED        (0x00U) /* Unlocked state */
+#define _80_CGC_PLL_LOCKED          (0x80U) /* Locked state */
+
+/*
+    FMP clock selection division register (MDIV)
+*/
+/* Division of PLL clock (fMP) */
+#define _00_CGC_FMP_DIV_DEFAULT     (0x00U) /* fMP (default) */
+#define _01_CGC_FMP_DIV_1           (0x01U) /* fMP/2^1 */
+#define _02_CGC_FMP_DIV_2           (0x02U) /* fMP/2^2 */
+#define _03_CGC_FMP_DIV_3           (0x03U) /* fMP/2^3 */
+#define _04_CGC_FMP_DIV_4           (0x04U) /* fMP/2^4 */
+#define _05_CGC_FMP_DIV_5           (0x05U) /* fMP/2^5 */
+#define _06_CGC_FMP_DIV_6           (0x06U) /* fMP/2^6 */
+
+/*
+    System clock control register (CKC)
+*/
+/* Status of CPU/peripheral hardware clock fCLK (CLS) */
+#define _00_CGC_CPUCLK_MAIN         (0x00U) /* main system clock (fMAIN) */
+#define _80_CGC_CPUCLK_SUB          (0x80U) /* subsystem clock (fSUB) */
+/* Selection of CPU/peripheral hardware clock fCLK (CSS) */
+#define _00_CGC_CPUCLK_SELMAIN      (0x00U) /* main system clock (fMAIN) */
+#define _40_CGC_CPUCLK_SELSUB       (0x40U) /* subsystem clock (fSUB) */
+/* Status of Main system clock fMAIN (MCS) */
+#define _00_CGC_MAINCLK_HIO         (0x00U) /* high-speed OCO clock (fIH) */
+#define _20_CGC_MAINCLK_HISYS       (0x20U) /* high-speed system clock (fMX) */
+/* Selection of Main system clock fMAIN (MCM0) */
+#define _00_CGC_MAINCLK_SELHIO      (0x00U) /* high-speed OCO clock (fIH) */
+#define _10_CGC_MAINCLK_SELHISYS    (0x10U) /* high-speed system clock (fMX) */
+
+/*
+    Operation speed mode control register (OSMC)
+*/
+/* Setting in subsystem clock HALT mode (RTCLPC) */
+#define _00_CGC_SUBINHALT_ON        (0x00U) /* enables supply of subsystem clock to peripheral functions */
+#define _80_CGC_SUBINHALT_OFF       (0x80U) /* stops supply to peripheral functions other than RTC and interval timer */
+/* RTC macro operation clock (WUTMMCK0) */
+#define _00_CGC_RTC_CLK_OTHER       (0x00U) /* Other than fIL */
+#define _10_CGC_RTC_CLK_FIL         (0x10U) /* use fIL clock */
+
+/*
+    Illegal memory access detection control register (IAWCTL)
+*/
+/* Illegal memory access detection control (IAWEN) */
+#define _00_CGC_ILLEGAL_ACCESS_OFF  (0x00U) /* disables illegal memory access detection */
+#define _80_CGC_ILLEGAL_ACCESS_ON   (0x80U) /* enables illegal memory access detection */
+/* RAM guard area (GRAM1, GRAM0) */
+#define _00_CGC_RAM_GUARD_OFF       (0x00U) /* invalid, it is possible to write RAM */
+#define _10_CGC_RAM_GUARD_AREA0     (0x10U) /* 128 bytes from RAM bottom address */
+#define _20_CGC_RAM_GUARD_AREA1     (0x20U) /* 256 bytes from RAM bottom address */
+#define _30_CGC_RAM_GUARD_AREA2     (0x30U) /* 512 bytes from RAM bottom address */
+/* PORT register guard (GPORT) */
+#define _00_CGC_PORT_GUARD_OFF      (0x00U) /* invalid, it is possible to write PORT register */
+#define _04_CGC_PORT_GUARD_ON       (0x04U) /* valid, it is impossible to write PORT register, but possible for read */
+/* Interrupt register guard (GINT) */
+#define _00_CGC_INT_GUARD_OFF       (0x00U) /* invalid, it is possible to write interrupt register */
+#define _02_CGC_INT_GUARD_ON        (0x02U) /* valid, it is impossible to write , but possible for read */
+/* CSC register guard (GCSC) */
+#define _00_CGC_CSC_GUARD_OFF       (0x00U) /* invalid, it is possible to write CSC register */
+#define _01_CGC_CSC_GUARD_ON        (0x01U) /* valid, it is impossible to write CSC register, but possible for read */
+
+/*
+    RTC clock selection register (RTCCL)
+*/
+/* Operation clock source selection for RTC (RTCCL7) */
+#define _00_CGC_RTC_FMX             (0x00U) /* RTC uses External Main clock (fMX) */
+#define _80_CGC_RTC_FIH             (0x80U) /* RTC uses Internal high speed clock (fIH) */
+/* Operation selection of RTC macro (RTCCL6,RTCCKS1 - RTCCKS0)  */
+#define _00_CGC_RTC_FSUB            (0x00U) /* RTC uses sub clock */
+#define _02_CGC_RTC_DIV128          (0x02U) /* RTC uses high-speed clock / 128 */
+#define _03_CGC_RTC_DIV256          (0x03U) /* RTC uses high-speed clock / 256 */
+#define _42_CGC_RTC_DIV122          (0x42U) /* RTC uses high-speed clock / 122 */
+#define _43_CGC_RTC_DIV244          (0x43U) /* RTC uses high-speed clock / 244 */
+
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+typedef enum
+{
+    HIOCLK, 
+    SYSX1CLK, 
+    SYSEXTCLK, 
+    SUBXT1CLK, 
+    SUBEXTCLK
+} clock_mode_t;
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+void R_CGC_Create(void);
+void R_CGC_Get_ResetSource(void);
+
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif

r_cg_cgc_user.c

@@ -0,0 +1,64 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_cgc_user.c
+* Version      : CodeGenerator for RL78/F14 V2.03.07.02 [08 Nov 2021]
+* Device(s)    : R5F10PPJ
+* Tool-Chain   : CCRL
+* Description  : This file implements device driver for CGC module.
+* Creation Date: 2026-08-03
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "r_cg_cgc.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+* Function Name: R_CGC_Get_ResetSource
+* Description  : This function process of Reset.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_CGC_Get_ResetSource(void)
+{
+    uint8_t reset_flag = RESF;
+    /* Start user code. Do not edit comment generated here */
+    /* End user code. Do not edit comment generated here */
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */

r_cg_macrodriver.h

@@ -0,0 +1,89 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_macrodriver.h
+* Version      : CodeGenerator for RL78/F14 V2.03.07.02 [08 Nov 2021]
+* Device(s)    : R5F10PPJ
+* Tool-Chain   : CCRL
+* Description  : This file implements general head file.
+* Creation Date: 2026-08-03
+***********************************************************************************************************************/
+
+#ifndef STATUS_H
+#define STATUS_H
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "iodefine.h"
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+#ifndef __TYPEDEF__
+#define DI      __DI
+#define EI      __EI
+#define HALT    __halt
+#define NOP     __nop
+#define STOP    __stop
+#define BRK     __brk
+
+/* Status list definition */
+#define MD_STATUSBASE       0x00U
+#define MD_OK               (MD_STATUSBASE + 0x00U) /* register setting OK */
+#define MD_SPT              (MD_STATUSBASE + 0x01U) /* IIC stop */
+#define MD_NACK             (MD_STATUSBASE + 0x02U) /* IIC no ACK */
+#define MD_BUSY1            (MD_STATUSBASE + 0x03U) /* busy 1 */
+#define MD_BUSY2            (MD_STATUSBASE + 0x04U) /* busy 2 */
+#define MD_OVERRUN          (MD_STATUSBASE + 0x05U) /* IIC OVERRUN occur */
+
+/* Error list definition */
+#define MD_ERRORBASE        0x80U
+#define MD_ERROR            (MD_ERRORBASE + 0x00U)  /* error */
+#define MD_ARGERROR         (MD_ERRORBASE + 0x01U)  /* error agrument input error */
+#define MD_ERROR1           (MD_ERRORBASE + 0x02U)  /* error 1 */
+#define MD_ERROR2           (MD_ERRORBASE + 0x03U)  /* error 2 */
+#define MD_ERROR3           (MD_ERRORBASE + 0x04U)  /* error 3 */
+#define MD_ERROR4           (MD_ERRORBASE + 0x05U)  /* error 4 */
+#define MD_DATAEXISTS       (MD_ERRORBASE + 0x06U)  /* data to be transferred next exists in TXBn register */
+#endif
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+#ifndef __TYPEDEF__
+typedef signed char         int8_t;
+typedef unsigned char       uint8_t;
+typedef signed short        int16_t;
+typedef unsigned short      uint16_t;
+typedef signed long         int32_t;
+typedef unsigned long       uint32_t;
+typedef unsigned short      MD_STATUS;
+#define __TYPEDEF__
+#endif
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+
+#endif

r_cg_port.c

@@ -0,0 +1,108 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_port.c
+* Version      : CodeGenerator for RL78/F14 V2.03.07.02 [08 Nov 2021]
+* Device(s)    : R5F10PPJ
+* Tool-Chain   : CCRL
+* Description  : This file implements device driver for PORT module.
+* Creation Date: 2026-08-03
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "r_cg_port.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+* Function Name: R_PORT_Create
+* Description  : This function initializes the Port I/O.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_PORT_Create(void)
+{
+    P0 = _01_Pn0_OUTPUT_1 | _00_Pn1_OUTPUT_0 | _00_Pn2_OUTPUT_0 | _08_Pn3_OUTPUT_1;
+    P1 = _01_Pn0_OUTPUT_1 | _08_Pn3_OUTPUT_1 | _10_Pn4_OUTPUT_1;
+    P3 = _01_Pn0_OUTPUT_1 | _04_Pn2_OUTPUT_1;
+    P4 = _00_Pn1_OUTPUT_0 | _00_Pn2_OUTPUT_0 | _00_Pn3_OUTPUT_0 | _00_Pn4_OUTPUT_0 | _00_Pn5_OUTPUT_0 |
+         _00_Pn6_OUTPUT_0 | _00_Pn7_OUTPUT_0;
+    P5 = _00_Pn0_OUTPUT_0 | _00_Pn1_OUTPUT_0 | _00_Pn2_OUTPUT_0 | _10_Pn4_OUTPUT_1 | _20_Pn5_OUTPUT_1 |
+         _40_Pn6_OUTPUT_1 | _80_Pn7_OUTPUT_1;
+    P6 = _00_Pn0_OUTPUT_0 | _00_Pn1_OUTPUT_0 | _00_Pn4_OUTPUT_0 | _00_Pn5_OUTPUT_0 | _00_Pn6_OUTPUT_0 |
+         _00_Pn7_OUTPUT_0;
+    P7 = _00_Pn0_OUTPUT_0 | _02_Pn1_OUTPUT_1 | _00_Pn2_OUTPUT_0 | _00_Pn3_OUTPUT_0 | _00_Pn4_OUTPUT_0 |
+         _00_Pn5_OUTPUT_0 | _00_Pn6_OUTPUT_0 | _00_Pn7_OUTPUT_0;
+    P9 = _00_Pn2_OUTPUT_0 | _00_Pn3_OUTPUT_0 | _00_Pn4_OUTPUT_0 | _00_Pn5_OUTPUT_0 | _00_Pn6_OUTPUT_0 |
+         _00_Pn7_OUTPUT_0;
+    P10 = _00_Pn0_OUTPUT_0 | _00_Pn1_OUTPUT_0 | _00_Pn2_OUTPUT_0 | _00_Pn3_OUTPUT_0 | _10_Pn4_OUTPUT_1 |
+          _20_Pn5_OUTPUT_1 | _40_Pn6_OUTPUT_1 | _80_Pn7_OUTPUT_1;
+    P12 = _00_Pn0_OUTPUT_0 | _00_Pn5_OUTPUT_0 | _00_Pn6_OUTPUT_0 | _00_Pn7_OUTPUT_0;
+    P13 = _00_Pn0_OUTPUT_0;
+    P15 = _00_Pn0_OUTPUT_0 | _00_Pn1_OUTPUT_0 | _00_Pn2_OUTPUT_0 | _00_Pn3_OUTPUT_0 | _10_Pn4_OUTPUT_1 |
+          _20_Pn5_OUTPUT_1 | _40_Pn6_OUTPUT_1 | _80_Pn7_OUTPUT_1;
+    POM6 = _04_POMn2_NCH_ON | _08_POMn3_NCH_ON;
+    POM7 = _01_POMn0_NCH_ON;
+    PMC7 = _00_PMCn0_DI_ON | _00_PMCn1_DI_ON | _00_PMCn2_DI_ON | _00_PMCn3_DI_ON | _00_PMCn4_DI_ON | _E0_PMC7_DEFAULT;
+    PMC12 = _00_PMCn0_DI_ON | _00_PMCn5_DI_ON | _DE_PMC12_DEFAULT;
+    PSRSEL = _00_PSR14_NORMAL | _00_PSR120_NORMAL | _00_PSR30_NORMAL | _00_PSR10_NORMAL;
+    ADPC = _04_ADPC_DI_ON;
+    PM0 = _00_PMn0_MODE_OUTPUT | _00_PMn1_MODE_OUTPUT | _00_PMn2_MODE_OUTPUT | _00_PMn3_MODE_OUTPUT | _F0_PM0_DEFAULT;
+    PM1 = _00_PMn0_MODE_OUTPUT | _02_PMn1_NOT_USE | _04_PMn2_NOT_USE | _00_PMn3_MODE_OUTPUT | _00_PMn4_MODE_OUTPUT |
+          _20_PMn5_NOT_USE | _40_PMn6_NOT_USE | _80_PMn7_NOT_USE;
+    PM3 = _00_PMn0_MODE_OUTPUT | _02_PMn1_NOT_USE | _00_PMn2_MODE_OUTPUT | _08_PMn3_NOT_USE | _10_PMn4_NOT_USE |
+          _E0_PM3_DEFAULT;
+    PM4 = _01_PMn0_NOT_USE | _00_PMn1_MODE_OUTPUT | _00_PMn2_MODE_OUTPUT | _00_PMn3_MODE_OUTPUT | _00_PMn4_MODE_OUTPUT |
+          _00_PMn5_MODE_OUTPUT | _00_PMn6_MODE_OUTPUT | _00_PMn7_MODE_OUTPUT;
+    PM5 = _00_PMn0_MODE_OUTPUT | _00_PMn1_MODE_OUTPUT | _00_PMn2_MODE_OUTPUT | _08_PMn3_NOT_USE | _00_PMn4_MODE_OUTPUT |
+          _00_PMn5_MODE_OUTPUT | _00_PMn6_MODE_OUTPUT | _00_PMn7_MODE_OUTPUT;
+    PM6 = _00_PMn0_MODE_OUTPUT | _00_PMn1_MODE_OUTPUT | _04_PMn2_NOT_USE | _08_PMn3_NOT_USE | _00_PMn4_MODE_OUTPUT |
+          _00_PMn5_MODE_OUTPUT | _00_PMn6_MODE_OUTPUT | _00_PMn7_MODE_OUTPUT;
+    PM7 = _00_PMn0_MODE_OUTPUT | _00_PMn1_MODE_OUTPUT | _00_PMn2_MODE_OUTPUT | _00_PMn3_MODE_OUTPUT |
+          _00_PMn4_MODE_OUTPUT | _00_PMn5_MODE_OUTPUT | _00_PMn6_MODE_OUTPUT | _00_PMn7_MODE_OUTPUT;
+    PM8 = _01_PMn0_NOT_USE | _02_PMn1_MODE_INPUT | _04_PMn2_MODE_INPUT | _08_PMn3_MODE_INPUT | _10_PMn4_MODE_INPUT |
+          _20_PMn5_MODE_INPUT | _40_PMn6_NOT_USE | _80_PMn7_NOT_USE;
+    PM9 = _01_PMn0_NOT_USE | _02_PMn1_NOT_USE | _00_PMn2_MODE_OUTPUT | _00_PMn3_MODE_OUTPUT | _00_PMn4_MODE_OUTPUT |
+          _00_PMn5_MODE_OUTPUT | _00_PMn6_MODE_OUTPUT | _00_PMn7_MODE_OUTPUT;
+    PM10 = _00_PMn0_MODE_OUTPUT | _00_PMn1_MODE_OUTPUT | _00_PMn2_MODE_OUTPUT | _00_PMn3_MODE_OUTPUT |
+           _00_PMn4_MODE_OUTPUT | _00_PMn5_MODE_OUTPUT | _00_PMn6_MODE_OUTPUT | _00_PMn7_MODE_OUTPUT;
+    PM12 = _00_PMn0_MODE_OUTPUT | _00_PMn5_MODE_OUTPUT | _00_PMn6_MODE_OUTPUT | _00_PMn7_MODE_OUTPUT | _1E_PM12_DEFAULT;
+    PM15 = _00_PMn0_MODE_OUTPUT | _00_PMn1_MODE_OUTPUT | _00_PMn2_MODE_OUTPUT | _00_PMn3_MODE_OUTPUT |
+           _00_PMn4_MODE_OUTPUT | _00_PMn5_MODE_OUTPUT | _00_PMn6_MODE_OUTPUT | _00_PMn7_MODE_OUTPUT;
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */

r_cg_port.h

@@ -0,0 +1,265 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_port.h
+* Version      : CodeGenerator for RL78/F14 V2.03.07.02 [08 Nov 2021]
+* Device(s)    : R5F10PPJ
+* Tool-Chain   : CCRL
+* Description  : This file implements device driver for PORT module.
+* Creation Date: 2026-08-03
+***********************************************************************************************************************/
+
+#ifndef PORT_H
+#define PORT_H
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+/*
+  Port Mode Register (PMm)
+*/
+/* Pmn pin I/O mode selection (PMm7 - PMm0) */
+#define _01_PMn0_NOT_USE            (0x01U) /* not use Pn0 as digital I/O */
+#define _01_PMn0_MODE_INPUT         (0x01U) /* use Pn0 as input mode */
+#define _00_PMn0_MODE_OUTPUT        (0x00U) /* use Pn0 as output mode */
+#define _02_PMn1_NOT_USE            (0x02U) /* not use Pn1 as digital I/O */
+#define _02_PMn1_MODE_INPUT         (0x02U) /* use Pn1 as input mode */
+#define _00_PMn1_MODE_OUTPUT        (0x00U) /* use Pn1 as output mode */
+#define _04_PMn2_NOT_USE            (0x04U) /* not use Pn2 as digital I/O */
+#define _04_PMn2_MODE_INPUT         (0x04U) /* use Pn2 as input mode */
+#define _00_PMn2_MODE_OUTPUT        (0x00U) /* use Pn2 as output mode */
+#define _08_PMn3_NOT_USE            (0x08U) /* not use Pn3 as digital I/O */
+#define _08_PMn3_MODE_INPUT         (0x08U) /* use Pn3 as input mode */
+#define _00_PMn3_MODE_OUTPUT        (0x00U) /* use Pn3 as output mode */
+#define _10_PMn4_NOT_USE            (0x10U) /* not use Pn4 as digital I/O */
+#define _10_PMn4_MODE_INPUT         (0x10U) /* use Pn4 as input mode */
+#define _00_PMn4_MODE_OUTPUT        (0x00U) /* use Pn4 as output mode */
+#define _20_PMn5_NOT_USE            (0x20U) /* not use Pn5 as digital I/O */
+#define _20_PMn5_MODE_INPUT         (0x20U) /* use Pn5 as input mode */
+#define _00_PMn5_MODE_OUTPUT        (0x00U) /* use Pn5 as output mode */
+#define _40_PMn6_NOT_USE            (0x40U) /* not use Pn6 as digital I/O */
+#define _40_PMn6_MODE_INPUT         (0x40U) /* use Pn6 as input mode */
+#define _00_PMn6_MODE_OUTPUT        (0x00U) /* use Pn6 as output mode */
+#define _80_PMn7_NOT_USE            (0x80U) /* not use Pn7 as digital I/O */
+#define _80_PMn7_MODE_INPUT         (0x80U) /* use Pn7 as input mode */
+#define _00_PMn7_MODE_OUTPUT        (0x00U) /* use Pn7 as output mode */
+
+/*
+  Port Register (Pm)
+*/
+/* Pmn pin data (Pm0 to Pm7) */
+#define _00_Pn0_OUTPUT_0            (0x00U) /* Pn0 output 0 */
+#define _01_Pn0_OUTPUT_1            (0x01U) /* Pn0 output 1 */
+#define _00_Pn1_OUTPUT_0            (0x00U) /* Pn1 output 0 */
+#define _02_Pn1_OUTPUT_1            (0x02U) /* Pn1 output 1 */
+#define _00_Pn2_OUTPUT_0            (0x00U) /* Pn2 output 0 */
+#define _04_Pn2_OUTPUT_1            (0x04U) /* Pn2 output 1 */
+#define _00_Pn3_OUTPUT_0            (0x00U) /* Pn3 output 0 */
+#define _08_Pn3_OUTPUT_1            (0x08U) /* Pn3 output 1 */
+#define _00_Pn4_OUTPUT_0            (0x00U) /* Pn4 output 0 */
+#define _10_Pn4_OUTPUT_1            (0x10U) /* Pn4 output 1 */
+#define _00_Pn5_OUTPUT_0            (0x00U) /* Pn5 output 0 */
+#define _20_Pn5_OUTPUT_1            (0x20U) /* Pn5 output 1 */
+#define _00_Pn6_OUTPUT_0            (0x00U) /* Pn6 output 0 */
+#define _40_Pn6_OUTPUT_1            (0x40U) /* Pn6 output 1 */
+#define _00_Pn7_OUTPUT_0            (0x00U) /* Pn7 output 0 */
+#define _80_Pn7_OUTPUT_1            (0x80U) /* Pn7 output 1 */
+
+/*
+  Pull-up Resistor Option Register (PUm)
+*/
+/* Pmn pin on-chip pull-up resistor selection (PUmn) */
+#define _00_PUn0_PULLUP_OFF         (0x00U) /* Pn0 pull-up resistor not connected */
+#define _01_PUn0_PULLUP_ON          (0x01U) /* Pn0 pull-up resistor connected */
+#define _00_PUn1_PULLUP_OFF         (0x00U) /* Pn1 pull-up resistor not connected */
+#define _02_PUn1_PULLUP_ON          (0x02U) /* Pn1 pull-up resistor connected */
+#define _00_PUn2_PULLUP_OFF         (0x00U) /* Pn2 Pull-up resistor not connected */
+#define _04_PUn2_PULLUP_ON          (0x04U) /* Pn2 pull-up resistor connected */
+#define _00_PUn3_PULLUP_OFF         (0x00U) /* Pn3 pull-up resistor not connected */
+#define _08_PUn3_PULLUP_ON          (0x08U) /* Pn3 pull-up resistor connected */
+#define _00_PUn4_PULLUP_OFF         (0x00U) /* Pn4 pull-up resistor not connected */
+#define _10_PUn4_PULLUP_ON          (0x10U) /* Pn4 pull-up resistor connected */
+#define _00_PUn5_PULLUP_OFF         (0x00U) /* Pn5 pull-up resistor not connected */
+#define _20_PUn5_PULLUP_ON          (0x20U) /* Pn5 pull-up resistor connected */
+#define _00_PUn6_PULLUP_OFF         (0x00U) /* Pn6 pull-up resistor not connected */
+#define _40_PUn6_PULLUP_ON          (0x40U) /* Pn6 pull-up resistor connected */
+#define _00_PUn7_PULLUP_OFF         (0x00U) /* Pn7 pull-up resistor not connected */
+#define _80_PUn7_PULLUP_ON          (0x80U) /* Pn7 pull-up resistor connected */
+
+/*
+  Port Input Mode Register (PIMm)
+*/
+/* Pmn pin input buffer selection (PIMmn) */
+#define _00_PIMn0_TTL_OFF           (0x00U) /* set Pn0 normal input buffer */
+#define _01_PIMn0_TTL_ON            (0x01U) /* set Pn0 TTL input buffer */
+#define _00_PIMn1_TTL_OFF           (0x00U) /* set Pn1 normal input buffer */
+#define _02_PIMn1_TTL_ON            (0x02U) /* set Pn1 TTL input buffer */
+#define _00_PIMn2_TTL_OFF           (0x00U) /* set Pn2 normal input buffer */
+#define _04_PIMn2_TTL_ON            (0x04U) /* set Pn2 TTL input buffer */
+#define _00_PIMn3_TTL_OFF           (0x00U) /* set Pn3 normal input buffer */
+#define _08_PIMn3_TTL_ON            (0x08U) /* set Pn3 TTL input buffer */
+#define _00_PIMn4_TTL_OFF           (0x00U) /* set Pn4 normal input buffer */
+#define _10_PIMn4_TTL_ON            (0x10U) /* set Pn4 TTL input buffer */
+#define _00_PIMn5_TTL_OFF           (0x00U) /* set Pn5 normal input buffer */
+#define _20_PIMn5_TTL_ON            (0x20U) /* set Pn5 TTL input buffer */
+#define _00_PIMn6_TTL_OFF           (0x00U) /* set Pn6 normal input buffer */
+#define _40_PIMn6_TTL_ON            (0x40U) /* set Pn6 TTL input buffer */
+#define _00_PIMn7_TTL_OFF           (0x00U) /* set Pn7 normal input buffer */
+#define _80_PIMn7_TTL_ON            (0x80U) /* set Pn7 TTL input buffer */
+
+/*
+  Port Input Threshold Control Register (PITHLm)
+*/
+/* Pmn pin input threshold selection (PITHLmn) */
+#define _00_PITHLn0_SCHMITT3_OFF    (0x00U) /* set Pn0 schmitt 1 input (default) */
+#define _01_PITHLn0_SCHMITT3_ON     (0x01U) /* set Pn0 schmitt 3 input */
+#define _00_PITHLn1_SCHMITT3_OFF    (0x00U) /* set Pn1 schmitt 1 input (default) */
+#define _02_PITHLn1_SCHMITT3_ON     (0x02U) /* set Pn1 schmitt 3 input */
+#define _00_PITHLn2_SCHMITT3_OFF    (0x00U) /* set Pn2 schmitt 1 input (default) */
+#define _04_PITHLn2_SCHMITT3_ON     (0x04U) /* set Pn2 schmitt 3 input */
+#define _00_PITHLn3_SCHMITT3_OFF    (0x00U) /* set Pn3 schmitt 1 input (default) */
+#define _08_PITHLn3_SCHMITT3_ON     (0x08U) /* set Pn3 schmitt 3 input */
+#define _00_PITHLn4_SCHMITT3_OFF    (0x00U) /* set Pn4 schmitt 1 input (default) */
+#define _10_PITHLn4_SCHMITT3_ON     (0x10U) /* set Pn4 schmitt 3 input */
+#define _00_PITHLn5_SCHMITT3_OFF    (0x00U) /* set Pn5 schmitt 1 input (default) */
+#define _20_PITHLn5_SCHMITT3_ON     (0x20U) /* set Pn5 schmitt 3 input */
+#define _00_PITHLn6_SCHMITT3_OFF    (0x00U) /* set Pn6 schmitt 1 input (default) */
+#define _40_PITHLn6_SCHMITT3_ON     (0x40U) /* set Pn6 schmitt 3 input */
+#define _00_PITHLn7_SCHMITT3_OFF    (0x00U) /* set Pn7 schmitt 1 input (default) */
+#define _80_PITHLn7_SCHMITT3_ON     (0x80U) /* set Pn7 schmitt 3 input */
+
+/*
+  Port Output Mode Register (POMm)
+*/
+/* Pmn pin output mode selection (POMmn) */
+#define _00_POMn0_NCH_OFF           (0x00U) /* set Pn0 output normal mode */
+#define _01_POMn0_NCH_ON            (0x01U) /* set Pn0 output N-ch open-drain mode */
+#define _00_POMn1_NCH_OFF           (0x00U) /* set Pn1 output normal mode */
+#define _02_POMn1_NCH_ON            (0x02U) /* set Pn1 output N-ch open-drain mode */
+#define _00_POMn2_NCH_OFF           (0x00U) /* set Pn2 output normal mode */
+#define _04_POMn2_NCH_ON            (0x04U) /* set Pn2 output N-ch open-drain mode */
+#define _00_POMn3_NCH_OFF           (0x00U) /* set Pn3 output normal mode */
+#define _08_POMn3_NCH_ON            (0x08U) /* set Pn3 output N-ch open-drain mode */
+#define _00_POMn4_NCH_OFF           (0x00U) /* set Pn4 output normal mode */
+#define _10_POMn4_NCH_ON            (0x10U) /* set Pn4 output N-ch open-drain mode */
+#define _00_POMn5_NCH_OFF           (0x00U) /* set Pn5 output normal mode */
+#define _20_POMn5_NCH_ON            (0x20U) /* set Pn5 output N-ch open-drain mode */
+#define _00_POMn6_NCH_OFF           (0x00U) /* set Pn6 output normal mode */
+#define _40_POMn6_NCH_ON            (0x40U) /* set Pn6 output N-ch open-drain mode */
+#define _00_POMn7_NCH_OFF           (0x00U) /* set Pn7 output normal mode */
+#define _80_POMn7_NCH_ON            (0x80U) /* set Pn7 output N-ch open-drain mode */
+
+/*
+  Port Operation Mode Register (PMCm)
+*/
+/* Pmn pin digital input buffer selection (PMCmn) */
+#define _01_PMCn0_NOT_USE           (0x01U) /* not use Pn0 digital input */
+#define _00_PMCn0_DI_ON             (0x00U) /* enable Pn0 digital input */
+#define _02_PMCn1_NOT_USE           (0x02U) /* not use Pn1 digital input */
+#define _00_PMCn1_DI_ON             (0x00U) /* enable Pn1 digital input */
+#define _04_PMCn2_NOT_USE           (0x04U) /* not use Pn2 digital input */
+#define _00_PMCn2_DI_ON             (0x00U) /* enable Pn2 digital input */
+#define _08_PMCn3_NOT_USE           (0x08U) /* not use Pn3 digital input */
+#define _00_PMCn3_DI_ON             (0x00U) /* enable Pn3 digital input */
+#define _10_PMCn4_NOT_USE           (0x10U) /* not use Pn4 digital input */
+#define _00_PMCn4_DI_ON             (0x00U) /* enable Pn4 digital input */
+#define _20_PMCn5_NOT_USE           (0x20U) /* not use Pn5 digital input */
+#define _00_PMCn5_DI_ON             (0x00U) /* enable Pn5 digital input */
+#define _40_PMCn6_NOT_USE           (0x40U) /* not use Pn6 digital input */
+#define _00_PMCn6_DI_ON             (0x00U) /* enable Pn6 digital input */
+#define _80_PMCn7_NOT_USE           (0x80U) /* not use Pn7 digital input */
+#define _00_PMCn7_DI_ON             (0x00U) /* enable Pn7 digital input */
+
+/*
+  Port output slew rate select register (PSRSEL)
+*/
+/* P140/PCLBUZ0 pin output mode selection (PSR140) */
+#define _00_PSR140_NORMAL           (0x00U) /* normal mode (5 V/5 ns) */
+#define _20_PSR140_SLOW             (0x20U) /* slow mode (25 V/5 ns (target) (TYP.)) */
+/* P14/SCK01/SCL01/TO06/TRDIOC0 pin output mode selection (PSR14) */
+#define _00_PSR14_NORMAL            (0x00U) /* normal mode (5 V/5 ns) */
+#define _10_PSR14_SLOW              (0x10U) /* slow mode (25 V/5 ns (target) (TYP.)) */
+/* P120/SO01/TO07/TRDIOD0 pin output mode selection (PSR120) */
+#define _00_PSR120_NORMAL           (0x00U) /* normal mode (5 V/5 ns) */
+#define _08_PSR120_SLOW             (0x08U) /* slow mode (25 V/5 ns (target) (TYP.)) */
+/* P30/TO01/TRDIOD1/SNZOUT0 pin output mode selection (PSR30) */
+#define _00_PSR30_NORMAL            (0x00U) /* normal mode (5 V/5 ns) */
+#define _04_PSR30_SLOW              (0x04U) /* slow mode (25 V/5 ns (target) (TYP.)) */
+/* P12/SO10/TO11/(TRDIOD0)/TXD1/SNZOUT3 pin output mode selection (PSR12) */
+#define _00_PSR12_NORMAL            (0x00U) /* normal mode (5 V/5 ns) */
+#define _02_PSR12_SLOW              (0x02U) /* slow mode (25 V/5 ns (target) (TYP.)) */
+/* P10/SCK10/TO13/TRJO0/SCL10/LTXD1/CTXD0 pin output mode selection (PSR10) */
+#define _00_PSR10_NORMAL            (0x00U) /* normal mode (5 V/5 ns) */
+#define _01_PSR10_SLOW              (0x01U) /* slow mode (25 V/5 ns (target) (TYP.)) */
+
+
+/*
+  AD port configuration register (ADPC)
+*/
+/* Analog input/digital input switching (ADPC4 - ADPC0) */
+#define _00_ADPC_DI_OFF             (0x00U) /* use P33, P34, P80 - P87, P90 - P97, P100 - P105 as analog input */
+#define _18_ADPC_DI_ON              (0x18U) /* use P105 as digital input */
+#define _17_ADPC_DI_ON              (0x17U) /* use P104 - P105 as digital input */
+#define _16_ADPC_DI_ON              (0x16U) /* use P103 - P105 as digital input */
+#define _15_ADPC_DI_ON              (0x15U) /* use P102 - P105 as digital input */
+#define _14_ADPC_DI_ON              (0x14U) /* use P101 - P105 as digital input */
+#define _13_ADPC_DI_ON              (0x13U) /* use P100 - P105 as digital input */
+#define _12_ADPC_DI_ON              (0x12U) /* use P97, P100 - P105 as digital input */
+#define _11_ADPC_DI_ON              (0x11U) /* use P96 - P97, P100 - P105 as digital input */
+#define _10_ADPC_DI_ON              (0x10U) /* use P95 - P97, P100 - P105 as digital input */
+#define _0F_ADPC_DI_ON              (0x0FU) /* use P94 - P97, P100 - P105 as digital input */
+#define _0E_ADPC_DI_ON              (0x0EU) /* use P93 - P97, P100 - P105 as digital input */
+#define _0D_ADPC_DI_ON              (0x0DU) /* use P92 - P97, P100 - P105 as digital input */
+#define _0C_ADPC_DI_ON              (0x0CU) /* use P91 - P97, P100 - P105 as digital input */
+#define _0B_ADPC_DI_ON              (0x0BU) /* use P90 - P97, P100 - P105 as digital input */
+#define _0A_ADPC_DI_ON              (0x0AU) /* use P87, P90 - P97, P100 - P105 as digital input */
+#define _09_ADPC_DI_ON              (0x09U) /* use P86 - P87, P90 - P97, P100 - P105 as digital input */
+#define _08_ADPC_DI_ON              (0x08U) /* use P85 - P87, P90 - P97, P100 - P105 as digital input */
+#define _07_ADPC_DI_ON              (0x07U) /* use P84 - P87, P90 - P97, P100 - P105 as digital input */
+#define _06_ADPC_DI_ON              (0x06U) /* use P83 - P87, P90 - P97, P100 - P105 as digital input */
+#define _05_ADPC_DI_ON              (0x05U) /* use P82 - P87, P90 - P97, P100 - P105 as digital input */
+#define _04_ADPC_DI_ON              (0x04U) /* use P81 - P87, P90 - P97, P100 - P105 as digital input */
+#define _03_ADPC_DI_ON              (0x03U) /* use P80 - P87, P90 - P97, P100 - P105 as digital input */
+#define _02_ADPC_DI_ON              (0x02U) /* use P34, P80 - P87, P90 - P97, P100 - P105 as digital input */
+#define _01_ADPC_DI_ON              (0x01U) /* use P33, P34, P80 - P87, P90 - P97, P100 - P105 as digital input */
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+#define _F0_PM0_DEFAULT             (0xF0U) /* PM0 default value */
+#define _E0_PM3_DEFAULT             (0xE0U) /* PM3 default value */
+#define _1E_PM12_DEFAULT            (0x1EU) /* PM12 default value */
+#define _FE_PM14_DEFAULT            (0xFEU) /* PM14 default value */
+#define _E0_PMC7_DEFAULT            (0xE0U) /* PMC7 default value */
+#define _DE_PMC12_DEFAULT           (0xDEU) /* PMC12 default value */
+
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+void R_PORT_Create(void);
+
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif

r_cg_port_user.c

@@ -0,0 +1,51 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_port_user.c
+* Version      : CodeGenerator for RL78/F14 V2.03.07.02 [08 Nov 2021]
+* Device(s)    : R5F10PPJ
+* Tool-Chain   : CCRL
+* Description  : This file implements device driver for PORT module.
+* Creation Date: 2026-08-03
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "r_cg_port.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */

r_cg_serial.c

@@ -0,0 +1,530 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_serial.c
+* Version      : CodeGenerator for RL78/F14 V2.03.07.02 [08 Nov 2021]
+* Device(s)    : R5F10PPJ
+* Tool-Chain   : CCRL
+* Description  : This file implements device driver for Serial module.
+* Creation Date: 2026-08-03
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "r_cg_serial.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+volatile uint8_t * gp_uart0_tx_address;        /* uart0 transmit buffer address */
+volatile uint16_t  g_uart0_tx_count;           /* uart0 transmit data number */
+volatile uint8_t * gp_uart0_rx_address;        /* uart0 receive buffer address */
+volatile uint16_t  g_uart0_rx_count;           /* uart0 receive data number */
+volatile uint16_t  g_uart0_rx_length;          /* uart0 receive data length */
+volatile uint8_t * gp_uart1_tx_address;        /* uart1 transmit buffer address */
+volatile uint16_t  g_uart1_tx_count;           /* uart1 transmit data number */
+volatile uint8_t * gp_uart1_rx_address;        /* uart1 receive buffer address */
+volatile uint16_t  g_uart1_rx_count;           /* uart1 receive data number */
+volatile uint16_t  g_uart1_rx_length;          /* uart1 receive data length */
+volatile uint8_t   g_iica0_master_status_flag; /* iica0 master flag */
+volatile uint8_t   g_iica0_slave_status_flag;  /* iica0 slave flag */
+volatile uint8_t * gp_iica0_rx_address;        /* iica0 receive buffer address */
+volatile uint16_t  g_iica0_rx_len;             /* iica0 receive data length */
+volatile uint16_t  g_iica0_rx_cnt;             /* iica0 receive data count */
+volatile uint8_t * gp_iica0_tx_address;        /* iica0 send buffer address */
+volatile uint16_t  g_iica0_tx_cnt;             /* iica0 send data count */
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+* Function Name: R_SAU0_Create
+* Description  : This function initializes the SAU0 module.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_SAU0_Create(void)
+{
+    SAU0EN = 1U;    /* supply SAU0 clock */
+    NOP();
+    NOP();
+    NOP();
+    NOP();
+    SPS0 = _0001_SAU_CK00_FCLK_1 | _0010_SAU_CK01_FCLK_1;
+    R_UART0_Create();
+}
+
+/***********************************************************************************************************************
+* Function Name: R_UART0_Create
+* Description  : This function initializes the UART0 module.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_UART0_Create(void)
+{
+    ST0 |= _0002_SAU_CH1_STOP_TRG_ON | _0001_SAU_CH0_STOP_TRG_ON;    /* disable UART0 receive and transmit */
+    STMK0 = 1U;    /* disable INTST0 interrupt */
+    STIF0 = 0U;    /* clear INTST0 interrupt flag */
+    SRMK0 = 1U;    /* disable INTSR0 interrupt */
+    SRIF0 = 0U;    /* clear INTSR0 interrupt flag */
+    /* Set INTST0 low priority */
+    STPR10 = 1U;
+    STPR00 = 1U;
+    /* Set INTSR0 low priority */
+    SRPR10 = 1U;
+    SRPR00 = 1U;
+    SMR00 = _0020_SAU_SMRMN_INITIALVALUE | _0000_SAU_CLOCK_SELECT_CK00 | _0000_SAU_TRIGGER_SOFTWARE |
+            _0002_SAU_MODE_UART | _0000_SAU_TRANSFER_END;
+    SCR00 = _8000_SAU_TRANSMISSION | _0000_SAU_PARITY_NONE | _0080_SAU_LSB | _0010_SAU_STOP_1 | _0007_SAU_LENGTH_8;
+    SDR00 = _8800_UART0_TRANSMIT_DIVISOR;
+    NFEN0 |= _01_SAU_RXD0_FILTER_ON;
+    SIR01 = _0004_SAU_SIRMN_FECTMN | _0002_SAU_SIRMN_PECTMN | _0001_SAU_SIRMN_OVCTMN;    /* clear error flag */
+    SMR01 = _0020_SAU_SMRMN_INITIALVALUE | _0000_SAU_CLOCK_SELECT_CK00 | _0100_SAU_TRIGGER_RXD | _0000_SAU_EDGE_FALL |
+            _0002_SAU_MODE_UART | _0000_SAU_TRANSFER_END;
+    SCR01 = _4000_SAU_RECEPTION | _0000_SAU_PARITY_NONE | _0080_SAU_LSB | _0010_SAU_STOP_1 | _0007_SAU_LENGTH_8;
+    SDR01 = _8800_UART0_RECEIVE_DIVISOR;
+    SO0 |= _0001_SAU_CH0_DATA_OUTPUT_1;
+    SOL0 |= _0000_SAU_CHANNEL0_NORMAL;    /* output level normal */
+    SOE0 |= _0001_SAU_CH0_OUTPUT_ENABLE;    /* enable UART0 output */
+    /* Set RxD0 pin */
+    PM1 |= 0x40U;
+    /* Set TxD0 pin */
+    P1 |= 0x20U;
+    PM1 &= 0xDFU;
+}
+
+/***********************************************************************************************************************
+* Function Name: R_UART0_Start
+* Description  : This function starts the UART0 module operation.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_UART0_Start(void)
+{
+    SO0 |= _0001_SAU_CH0_DATA_OUTPUT_1;    /* output level normal */
+    SOE0 |= _0001_SAU_CH0_OUTPUT_ENABLE;    /* enable UART0 output */
+    SS0 |= _0002_SAU_CH1_START_TRG_ON | _0001_SAU_CH0_START_TRG_ON;    /* enable UART0 receive and transmit */
+    STIF0 = 0U;    /* clear INTST0 interrupt flag */
+    SRIF0 = 0U;    /* clear INTSR0 interrupt flag */
+    STMK0 = 0U;    /* enable INTST0 interrupt */
+    SRMK0 = 0U;    /* enable INTSR0 interrupt */
+}
+
+/***********************************************************************************************************************
+* Function Name: R_UART0_Stop
+* Description  : This function stops the UART0 module operation.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_UART0_Stop(void)
+{
+    STMK0 = 1U;    /* disable INTST0 interrupt */
+    SRMK0 = 1U;    /* disable INTSR0 interrupt */
+    ST0 |= _0002_SAU_CH1_STOP_TRG_ON | _0001_SAU_CH0_STOP_TRG_ON;    /* disable UART0 receive and transmit */
+    SOE0 &= ~_0001_SAU_CH0_OUTPUT_ENABLE;    /* disable UART0 output */
+    STIF0 = 0U;    /* clear INTST0 interrupt flag */
+    SRIF0 = 0U;    /* clear INTSR0 interrupt flag */
+}
+
+/***********************************************************************************************************************
+* Function Name: R_UART0_Receive
+* Description  : This function receives UART0 data.
+* Arguments    : rx_buf -
+*                    receive buffer pointer
+*                rx_num -
+*                    buffer size
+* Return Value : status -
+*                    MD_OK or MD_ARGERROR
+***********************************************************************************************************************/
+MD_STATUS R_UART0_Receive(uint8_t * const rx_buf, uint16_t rx_num)
+{
+    MD_STATUS status = MD_OK;
+
+    if (rx_num < 1U)
+    {
+        status = MD_ARGERROR;
+    }
+    else
+    {
+        g_uart0_rx_count = 0U;
+        g_uart0_rx_length = rx_num;
+        gp_uart0_rx_address = rx_buf;
+    }
+
+    return (status);
+}
+
+/***********************************************************************************************************************
+* Function Name: R_UART0_Send
+* Description  : This function sends UART0 data.
+* Arguments    : tx_buf -
+*                    transfer buffer pointer
+*                tx_num -
+*                    buffer size
+* Return Value : status -
+*                    MD_OK or MD_ARGERROR
+***********************************************************************************************************************/
+MD_STATUS R_UART0_Send(uint8_t * const tx_buf, uint16_t tx_num)
+{
+    MD_STATUS status = MD_OK;
+
+    if (tx_num < 1U)
+    {
+        status = MD_ARGERROR;
+    }
+    else
+    {
+        gp_uart0_tx_address = tx_buf;
+        g_uart0_tx_count = tx_num;
+        STMK0 = 1U;    /* disable INTST0 interrupt */
+        SDR00L = *gp_uart0_tx_address;
+        gp_uart0_tx_address++;
+        g_uart0_tx_count--;
+        STMK0 = 0U;    /* enable INTST0 interrupt */
+    }
+
+    return (status);
+}
+
+/***********************************************************************************************************************
+* Function Name: R_SAU1_Create
+* Description  : This function initializes the SAU1 module.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_SAU1_Create(void)
+{
+    SAU1EN = 1U;    /* supply SAU1 clock */
+    NOP();
+    NOP();
+    NOP();
+    NOP();
+    SPS1 = _0001_SAU_CK00_FCLK_1 | _0010_SAU_CK01_FCLK_1;
+    R_UART1_Create();
+}
+
+/***********************************************************************************************************************
+* Function Name: R_UART1_Create
+* Description  : This function initializes the UART1 module.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_UART1_Create(void)
+{
+    ST1 |= _0002_SAU_CH1_STOP_TRG_ON | _0001_SAU_CH0_STOP_TRG_ON;    /* disable UART1 receive and transmit */
+    STMK1 = 1U;    /* disable INTST1 interrupt */
+    STIF1 = 0U;    /* clear INTST1 interrupt flag */
+    SRMK1 = 1U;    /* disable INTSR1 interrupt */
+    SRIF1 = 0U;    /* clear INTSR1 interrupt flag */
+    /* Set INTST1 low priority */
+    STPR11 = 1U;
+    STPR01 = 1U;
+    /* Set INTSR1 low priority */
+    SRPR11 = 1U;
+    SRPR01 = 1U;
+    SMR10 = _0020_SAU_SMRMN_INITIALVALUE | _0000_SAU_CLOCK_SELECT_CK00 | _0000_SAU_TRIGGER_SOFTWARE |
+            _0002_SAU_MODE_UART | _0000_SAU_TRANSFER_END;
+    SCR10 = _8000_SAU_TRANSMISSION | _0000_SAU_PARITY_NONE | _0080_SAU_LSB | _0010_SAU_STOP_1 | _0007_SAU_LENGTH_8;
+    SDR10 = _8800_UART1_TRANSMIT_DIVISOR;
+    NFEN0 |= _04_SAU_RXD1_FILTER_ON;
+    SIR11 = _0004_SAU_SIRMN_FECTMN | _0002_SAU_SIRMN_PECTMN | _0001_SAU_SIRMN_OVCTMN;    /* clear error flag */
+    SMR11 = _0020_SAU_SMRMN_INITIALVALUE | _0000_SAU_CLOCK_SELECT_CK00 | _0100_SAU_TRIGGER_RXD | _0000_SAU_EDGE_FALL |
+            _0002_SAU_MODE_UART | _0000_SAU_TRANSFER_END;
+    SCR11 = _4000_SAU_RECEPTION | _0000_SAU_PARITY_NONE | _0080_SAU_LSB | _0010_SAU_STOP_1 | _0007_SAU_LENGTH_8;
+    SDR11 = _8800_UART1_RECEIVE_DIVISOR;
+    SO1 |= _0001_SAU_CH0_DATA_OUTPUT_1;
+    SOL1 |= _0000_SAU_CHANNEL0_NORMAL;    /* output level normal */
+    SOE1 |= _0001_SAU_CH0_OUTPUT_ENABLE;    /* enable UART1 output */
+    /* Set RxD1 pin */
+    PM1 |= 0x02U;
+    /* Set TxD1 pin */
+    P1 |= 0x04U;
+    PM1 &= 0xFBU;
+}
+
+/***********************************************************************************************************************
+* Function Name: R_UART1_Start
+* Description  : This function starts the UART1 module operation.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_UART1_Start(void)
+{
+    SO1 |= _0001_SAU_CH0_DATA_OUTPUT_1;    /* output level normal */
+    SOE1 |= _0001_SAU_CH0_OUTPUT_ENABLE;    /* enable UART1 output */
+    SS1 |= _0002_SAU_CH1_START_TRG_ON | _0001_SAU_CH0_START_TRG_ON;    /* enable UART1 receive and transmit */
+    STIF1 = 0U;    /* clear INTST1 interrupt flag */
+    SRIF1 = 0U;    /* clear INTSR1 interrupt flag */
+    STMK1 = 0U;    /* enable INTST1 interrupt */
+    SRMK1 = 0U;    /* enable INTSR1 interrupt */
+}
+
+/***********************************************************************************************************************
+* Function Name: R_UART1_Stop
+* Description  : This function stops the UART1 module operation.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_UART1_Stop(void)
+{
+    STMK1 = 1U;    /* disable INTST1 interrupt */
+    SRMK1 = 1U;    /* disable INTSR1 interrupt */
+    ST1 |= _0002_SAU_CH1_STOP_TRG_ON | _0001_SAU_CH0_STOP_TRG_ON;    /* disable UART1 receive and transmit */
+    SOE1 &= ~_0001_SAU_CH0_OUTPUT_ENABLE;    /* disable UART1 output */
+    STIF1 = 0U;    /* clear INTST1 interrupt flag */
+    SRIF1 = 0U;    /* clear INTSR1 interrupt flag */
+}
+
+/***********************************************************************************************************************
+* Function Name: R_UART1_Receive
+* Description  : This function receives UART1 data.
+* Arguments    : rx_buf -
+*                    receive buffer pointer
+*                rx_num -
+*                    buffer size
+* Return Value : status -
+*                    MD_OK or MD_ARGERROR
+***********************************************************************************************************************/
+MD_STATUS R_UART1_Receive(uint8_t * const rx_buf, uint16_t rx_num)
+{
+    MD_STATUS status = MD_OK;
+
+    if (rx_num < 1U)
+    {
+        status = MD_ARGERROR;
+    }
+    else
+    {
+        g_uart1_rx_count = 0U;
+        g_uart1_rx_length = rx_num;
+        gp_uart1_rx_address = rx_buf;
+    }
+
+    return (status);
+}
+
+/***********************************************************************************************************************
+* Function Name: R_UART1_Send
+* Description  : This function sends UART1 data.
+* Arguments    : tx_buf -
+*                    transfer buffer pointer
+*                tx_num -
+*                    buffer size
+* Return Value : status -
+*                    MD_OK or MD_ARGERROR
+***********************************************************************************************************************/
+MD_STATUS R_UART1_Send(uint8_t * const tx_buf, uint16_t tx_num)
+{
+    MD_STATUS status = MD_OK;
+
+    if (tx_num < 1U)
+    {
+        status = MD_ARGERROR;
+    }
+    else
+    {
+        gp_uart1_tx_address = tx_buf;
+        g_uart1_tx_count = tx_num;
+        STMK1 = 1U;    /* disable INTST1 interrupt */
+        SDR10L = *gp_uart1_tx_address;
+        gp_uart1_tx_address++;
+        g_uart1_tx_count--;
+        STMK1 = 0U;    /* enable INTST1 interrupt */
+    }
+
+    return (status);
+}
+
+/***********************************************************************************************************************
+* Function Name: R_IICA0_Create
+* Description  : This function initializes the IICA0 module.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_IICA0_Create(void)
+{
+    IICA0EN = 1U; /* supply IICA0 clock */
+    IICE0 = 0U; /* disable IICA0 operation */
+    IICAMK0 = 1U; /* disable INTIICA0 interrupt */
+    IICAIF0 = 0U; /* clear INTIICA0 interrupt flag */
+    /* Set INTIICA0 low priority */
+    IICAPR10 = 1U;
+    IICAPR00 = 1U;
+    /* Set SCLA0, SDAA0 pin */
+    P6 &= 0xF3U;
+    PM6 |= 0x0CU;
+    SMC0 = 0U;
+    IICWL0 = _4C_IICA0_IICWL_VALUE;
+    IICWH0 = _55_IICA0_IICWH_VALUE;
+    IICCTL01 |= _01_IICA_fCLK_HALF;
+    SVA0 = _10_IICA0_MASTERADDRESS;
+    STCEN0 = 1U;
+    IICRSV0 = 1U;
+    SPIE0 = 0U;
+    WTIM0 = 1U;
+    ACKE0 = 1U;
+    IICAMK0 = 0U;
+    IICE0 = 1U;
+    LREL0 = 1U;
+    /* Set SCLA0, SDAA0 pin */
+    PM6 &= 0xF3U;
+}
+
+/***********************************************************************************************************************
+* Function Name: R_IICA0_Stop
+* Description  : This function stops IICA0 module operation.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_IICA0_Stop(void)
+{
+    IICE0 = 0U;    /* disable IICA0 operation */
+}
+
+/***********************************************************************************************************************
+* Function Name: R_IICA0_StopCondition
+* Description  : This function sets IICA0 stop condition flag.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_IICA0_StopCondition(void)
+{
+    SPT0 = 1U;     /* set stop condition flag */
+}
+
+/***********************************************************************************************************************
+* Function Name: R_IICA0_Master_Send
+* Description  : This function starts to send data as master mode.
+* Arguments    : adr -
+*                    send address
+*                tx_buf -
+*                    transfer buffer pointer
+*                tx_num -
+*                    buffer size
+*                wait -
+*                    wait for start condition
+* Return Value : status -
+*                    MD_OK or MD_ERROR1 or MD_ERROR2
+***********************************************************************************************************************/
+MD_STATUS R_IICA0_Master_Send(uint8_t adr, uint8_t * const tx_buf, uint16_t tx_num, uint8_t wait)
+{
+    MD_STATUS status = MD_OK;
+
+    IICAMK0 = 1U;  /* disable INTIICA0 interrupt */
+
+    if ((1U == IICBSY0) && (0U == MSTS0))
+    {
+        /* Check bus busy */
+        IICAMK0 = 0U;  /* enable INTIICA0 interrupt */
+        status = MD_ERROR1;
+    }
+    else
+    {
+        STT0 = 1U; /* send IICA0 start condition */
+        IICAMK0 = 0U;  /* enable INTIICA0 interrupt */
+
+        /* Wait */
+        while (wait--)
+        {
+            ;
+        }
+
+        if (0U == STD0)
+        {
+            status = MD_ERROR2;
+        }
+
+        /* Set parameter */
+        g_iica0_tx_cnt = tx_num;
+        gp_iica0_tx_address = tx_buf;
+        g_iica0_master_status_flag = _00_IICA_MASTER_FLAG_CLEAR;
+        adr &= (uint8_t)~0x01U; /* set send mode */
+        IICA0 = adr; /* send address */
+    }
+
+    return (status);
+}
+
+/***********************************************************************************************************************
+* Function Name: R_IICA0_Master_Receive
+* Description  : This function starts to receive IICA0 data as master mode.
+* Arguments    : adr -
+*                    receive address
+*                rx_buf -
+*                    receive buffer pointer
+*                rx_num -
+*                    buffer size
+*                wait -
+*                    wait for start condition
+* Return Value : status -
+*                    MD_OK or MD_ERROR1 or MD_ERROR2
+***********************************************************************************************************************/
+MD_STATUS R_IICA0_Master_Receive(uint8_t adr, uint8_t * const rx_buf, uint16_t rx_num, uint8_t wait)
+{
+    MD_STATUS status = MD_OK;
+
+    IICAMK0 = 1U;  /* disable INTIIA0 interrupt */
+
+    if ((1U == IICBSY0) && (0U == MSTS0))
+    {
+        /* Check bus busy */
+        IICAMK0 = 0U;  /* enable INTIIA0 interrupt */
+        status = MD_ERROR1;
+    }
+    else
+    {
+        STT0 = 1U; /* set IICA0 start condition */
+        IICAMK0 = 0U;  /* enable INTIIA0 interrupt */
+
+        /* Wait */
+        while (wait--)
+        {
+            ;
+        }
+
+        if (0U == STD0)
+        {
+            status = MD_ERROR2;
+        }
+
+        /* Set parameter */
+        g_iica0_rx_len = rx_num;
+        g_iica0_rx_cnt = 0U;
+        gp_iica0_rx_address = rx_buf;
+        g_iica0_master_status_flag  = _00_IICA_MASTER_FLAG_CLEAR;
+        adr |= 0x01U; /* set receive mode */
+        IICA0 = adr; /* receive address */
+    }
+
+    return (status);
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */

r_cg_serial.h

@@ -0,0 +1,399 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_serial.h
+* Version      : CodeGenerator for RL78/F14 V2.03.07.02 [08 Nov 2021]
+* Device(s)    : R5F10PPJ
+* Tool-Chain   : CCRL
+* Description  : This file implements device driver for Serial module.
+* Creation Date: 2026-08-03
+***********************************************************************************************************************/
+
+#ifndef SERIAL_H
+#define SERIAL_H
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+/*
+    Serial Clock Select Register m (SPSm)
+*/
+/* Section of operation clock (CKm0) (PRSm03 - PRSm00) */
+#define _0000_SAU_CK00_FCLK_0                    (0x0000U) /* ck00 - fCLK */
+#define _0001_SAU_CK00_FCLK_1                    (0x0001U) /* ck00 - fCLK/2^1 */
+#define _0002_SAU_CK00_FCLK_2                    (0x0002U) /* ck00 - fCLK/2^2 */
+#define _0003_SAU_CK00_FCLK_3                    (0x0003U) /* ck00 - fCLK/2^3 */
+#define _0004_SAU_CK00_FCLK_4                    (0x0004U) /* ck00 - fCLK/2^4 */
+#define _0005_SAU_CK00_FCLK_5                    (0x0005U) /* ck00 - fCLK/2^5 */
+#define _0006_SAU_CK00_FCLK_6                    (0x0006U) /* ck00 - fCLK/2^6 */
+#define _0007_SAU_CK00_FCLK_7                    (0x0007U) /* ck00 - fCLK/2^7 */
+#define _0008_SAU_CK00_FCLK_8                    (0x0008U) /* ck00 - fCLK/2^8 */
+#define _0009_SAU_CK00_FCLK_9                    (0x0009U) /* ck00 - fCLK/2^9 */
+#define _000A_SAU_CK00_FCLK_10                   (0x000AU) /* ck00 - fCLK/2^10 */
+#define _000B_SAU_CK00_FCLK_11                   (0x000BU) /* ck00 - fCLK/2^11 */
+#define _000C_SAU_CK00_FCLK_12                   (0x000CU) /* ck00 - fCLK/2^12 */
+#define _000D_SAU_CK00_FCLK_13                   (0x000DU) /* ck00 - fCLK/2^13 */
+#define _000E_SAU_CK00_FCLK_14                   (0x000EU) /* ck00 - fCLK/2^14 */
+#define _000F_SAU_CK00_FCLK_15                   (0x000FU) /* ck00 - fCLK/2^15 */
+/* Section of operation clock (CKm1) (PRSm13 - PRSm10) */
+#define _0000_SAU_CK01_FCLK_0                    (0x0000U) /* ck01 - fCLK */
+#define _0010_SAU_CK01_FCLK_1                    (0x0010U) /* ck01 - fCLK/2^1 */
+#define _0020_SAU_CK01_FCLK_2                    (0x0020U) /* ck01 - fCLK/2^2 */
+#define _0030_SAU_CK01_FCLK_3                    (0x0030U) /* ck01 - fCLK/2^3 */
+#define _0040_SAU_CK01_FCLK_4                    (0x0040U) /* ck01 - fCLK/2^4 */
+#define _0050_SAU_CK01_FCLK_5                    (0x0050U) /* ck01 - fCLK/2^5 */
+#define _0060_SAU_CK01_FCLK_6                    (0x0060U) /* ck01 - fCLK/2^6 */
+#define _0070_SAU_CK01_FCLK_7                    (0x0070U) /* ck01 - fCLK/2^7 */
+#define _0080_SAU_CK01_FCLK_8                    (0x0080U) /* ck01 - fCLK/2^8 */
+#define _0090_SAU_CK01_FCLK_9                    (0x0090U) /* ck01 - fCLK/2^9 */
+#define _00A0_SAU_CK01_FCLK_10                   (0x00A0U) /* ck01 - fCLK/2^10 */
+#define _00B0_SAU_CK01_FCLK_11                   (0x00B0U) /* ck01 - fCLK/2^11 */
+#define _00C0_SAU_CK01_FCLK_12                   (0x00C0U) /* ck01 - fCLK/2^12 */
+#define _00D0_SAU_CK01_FCLK_13                   (0x00D0U) /* ck01 - fCLK/2^13 */
+#define _00E0_SAU_CK01_FCLK_14                   (0x00E0U) /* ck01 - fCLK/2^14 */
+#define _00F0_SAU_CK01_FCLK_15                   (0x00F0U) /* ck01 - fCLK/2^15 */
+
+/*
+    Serial Mode Register mn (SMRmn)
+*/
+#define _0020_SAU_SMRMN_INITIALVALUE             (0x0020U)
+/* Selection of macro clock (MCK) of channel n (CKSmn) */
+#define _0000_SAU_CLOCK_SELECT_CK00              (0x0000U) /* operation clock CK0 set by PRS register */ 
+#define _8000_SAU_CLOCK_SELECT_CK01              (0x8000U) /* operation clock CK1 set by PRS register */
+/* Selection of transfer clock (TCLK) of channel n (CCSmn) */
+#define _0000_SAU_CLOCK_MODE_CKS                 (0x0000U) /* divided operation clock MCK specified by CKSmn bit */  
+#define _4000_SAU_CLOCK_MODE_TI0N                (0x4000U) /* clock input from SCK pin (slave transfer in CSI mode) */
+/* Selection of start trigger source (STSmn) */
+#define _0000_SAU_TRIGGER_SOFTWARE               (0x0000U) /* only software trigger is valid */
+#define _0100_SAU_TRIGGER_RXD                    (0x0100U) /* valid edge of RXD pin */
+/* Controls inversion of level of receive data of channel n in UART mode (SISmn0) */
+#define _0000_SAU_EDGE_FALL                      (0x0000U) /* falling edge is detected as the start bit */
+#define _0040_SAU_EDGE_RISING                    (0x0040U) /* rising edge is detected as the start bit */
+/* Setting of operation mode of channel n (MDmn2, MDmn1) */
+#define _0000_SAU_MODE_CSI                       (0x0000U) /* CSI mode */
+#define _0002_SAU_MODE_UART                      (0x0002U) /* UART mode */
+#define _0004_SAU_MODE_IIC                       (0x0004U) /* simplified IIC mode */
+/* Selection of interrupt source of channel n (MDmn0) */
+#define _0000_SAU_TRANSFER_END                   (0x0000U) /* transfer end interrupt */
+#define _0001_SAU_BUFFER_EMPTY                   (0x0001U) /* buffer empty interrupt */
+
+/*
+    Serial Communication Operation Setting Register mn (SCRmn)
+*/
+/* Setting of operation mode of channel n (TXEmn, RXEmn) */
+#define _0000_SAU_NOT_COMMUNICATION              (0x0000U) /* does not start communication */
+#define _4000_SAU_RECEPTION                      (0x4000U) /* reception only */
+#define _8000_SAU_TRANSMISSION                   (0x8000U) /* transmission only */
+#define _C000_SAU_RECEPTION_TRANSMISSION         (0xC000U) /* reception and transmission */
+/* Selection of data and clock phase in CSI mode (DAPmn, CKPmn) */
+#define _0000_SAU_TIMING_1                       (0x0000U) /* type 1 */
+#define _1000_SAU_TIMING_2                       (0x1000U) /* type 2 */
+#define _2000_SAU_TIMING_3                       (0x2000U) /* type 3 */
+#define _3000_SAU_TIMING_4                       (0x3000U) /* type 4 */
+/* Setting of parity bit in UART mode (PTCmn1 - PTCmn0) */
+#define _0000_SAU_PARITY_NONE                    (0x0000U) /* none parity */
+#define _0100_SAU_PARITY_ZERO                    (0x0100U) /* zero parity */
+#define _0200_SAU_PARITY_EVEN                    (0x0200U) /* even parity */
+#define _0300_SAU_PARITY_ODD                     (0x0300U) /* odd parity */
+/* Selection of data transfer sequence in CSI and UART modes (DIRmn) */
+#define _0000_SAU_MSB                            (0x0000U) /* MSB */
+#define _0080_SAU_LSB                            (0x0080U) /* LSB */
+/* Setting of stop bit in UART mode (SLCmn1, SLCmn0) */
+#define _0000_SAU_STOP_NONE                      (0x0000U) /* none stop bit */
+#define _0010_SAU_STOP_1                         (0x0010U) /* 1 stop bit */
+#define _0020_SAU_STOP_2                         (0x0020U) /* 2 stop bits */
+/* Setting of data length in CSI and UART modes (DLSmn3 - DLSmn0) (m = 0, 1) */
+#define _0006_SAU_LENGTH_7                       (0x0006U) /* 07-bit data length */
+#define _0007_SAU_LENGTH_8                       (0x0007U) /* 08-bit data length */
+#define _0008_SAU_LENGTH_9                       (0x0008U) /* 09-bit data length */
+#define _0009_SAU_LENGTH_10                      (0x0009U) /* 10-bit data length */
+#define _000A_SAU_LENGTH_11                      (0x000AU) /* 11-bit data length */
+#define _000B_SAU_LENGTH_12                      (0x000BU) /* 12-bit data length */
+#define _000C_SAU_LENGTH_13                      (0x000CU) /* 13-bit data length */
+#define _000D_SAU_LENGTH_14                      (0x000DU) /* 14-bit data length */
+#define _000E_SAU_LENGTH_15                      (0x000EU) /* 15-bit data length */
+#define _000F_SAU_LENGTH_16                      (0x000FU) /* 16-bit data length */
+
+/*
+    Serial Output Level Register m (SOLm)
+*/
+/* Selects inversion of the level of the transmit data of channel n in UART mode */
+#define _0000_SAU_CHANNEL0_NORMAL                (0x0000U) /* normal bit level */
+#define _0001_SAU_CHANNEL0_INVERTED              (0x0001U) /* inverted bit level */
+
+/*
+    Noise Filter Enable Register 0 (NFEN0)
+*/
+/* Use of noise filter */
+#define _00_SAU_RXD1_FILTER_OFF                  (0x00U)   /* noise filter off */
+#define _04_SAU_RXD1_FILTER_ON                   (0x04U)   /* noise filter on */
+#define _00_SAU_RXD0_FILTER_OFF                  (0x00U)   /* noise filter off */
+#define _01_SAU_RXD0_FILTER_ON                   (0x01U)   /* noise filter on */
+
+/*
+    Format of Serial Status Register mn (SSRmn)
+*/
+/* Communication status indication flag of channel n (TSFmn) */
+#define _0040_SAU_UNDER_EXECUTE                  (0x0040U) /* communication is under execution */
+/* Buffer register status indication flag of channel n (BFFmn) */
+#define _0020_SAU_VALID_STORED                   (0x0020U) /* valid data is stored in the SDRmn register */
+/* Framing error detection flag of channel n (FEFmn) */
+#define _0004_SAU_FRAM_ERROR                     (0x0004U) /* a framing error occurs during UART reception */
+/* Parity error detection flag of channel n (PEFmn) */
+#define _0002_SAU_PARITY_ERROR                   (0x0002U) /* a parity error occurs or ACK is not detected */
+/* Overrun error detection flag of channel n (OVFmn) */
+#define _0001_SAU_OVERRUN_ERROR                  (0x0001U) /* an overrun error occurs */
+
+/*
+    Serial Channel Start Register m (SSm)
+*/
+/* Operation start trigger of channel 0 (SSm0) */
+#define _0000_SAU_CH0_START_TRG_OFF              (0x0000U) /* no trigger operation */
+#define _0001_SAU_CH0_START_TRG_ON               (0x0001U) /* sets SEm0 to 1 and enters the communication wait status */
+/* Operation start trigger of channel 1 (SSm1) */
+#define _0000_SAU_CH1_START_TRG_OFF              (0x0000U) /* no trigger operation */
+#define _0002_SAU_CH1_START_TRG_ON               (0x0002U) /* sets SEm1 to 1 and enters the communication wait status */
+
+/*
+    Serial Channel Stop Register m (STm)
+*/
+/* Operation stop trigger of channel 0 (STm0) */
+#define _0000_SAU_CH0_STOP_TRG_OFF               (0x0000U) /* no trigger operation */
+#define _0001_SAU_CH0_STOP_TRG_ON                (0x0001U) /* operation is stopped (stop trigger is generated) */
+/* Operation stop trigger of channel 1 (STm1) */
+#define _0000_SAU_CH1_STOP_TRG_OFF               (0x0000U) /* no trigger operation */
+#define _0002_SAU_CH1_STOP_TRG_ON                (0x0002U) /* operation is stopped (stop trigger is generated) */
+
+/*
+    Format of Serial Flag Clear Trigger Register mn (SIRmn)
+*/
+/* Clear trigger of overrun error flag of channel n (OVCTmn) */
+#define _0001_SAU_SIRMN_OVCTMN                   (0x0001U)
+/* Clear trigger of parity error flag of channel n (PECTmn) */
+#define _0002_SAU_SIRMN_PECTMN                   (0x0002U)
+/* Clear trigger of framing error of channel n (FECTMN) */
+#define _0004_SAU_SIRMN_FECTMN                   (0x0004U)
+
+/*
+    Serial Output Enable Register m (SOEm)
+*/
+/* Serial output enable/disable of channel 0 (SOEm0) */
+#define _0001_SAU_CH0_OUTPUT_ENABLE              (0x0001U) /* enables output by serial communication operation */
+#define _0000_SAU_CH0_OUTPUT_DISABLE             (0x0000U) /* stops output by serial communication operation */
+/* Serial output enable/disable of channel 1 (SOEm1) */
+#define _0002_SAU_CH1_OUTPUT_ENABLE              (0x0002U) /* enables output by serial communication operation */
+#define _0000_SAU_CH1_OUTPUT_DISABLE             (0x0000U) /* stops output by serial communication operation */
+
+/*
+    Serial Output Register m (SOm)
+*/
+/* Serial data output of channel 0 (SOm0) */
+#define _0000_SAU_CH0_DATA_OUTPUT_0              (0x0000U) /* Serial data output value is "0" */
+#define _0001_SAU_CH0_DATA_OUTPUT_1              (0x0001U) /* Serial data output value is "1" */
+/* Serial data output of channel 1 (SOm1) */
+#define _0000_SAU_CH1_DATA_OUTPUT_0              (0x0000U) /* Serial data output value is "0" */
+#define _0002_SAU_CH1_DATA_OUTPUT_1              (0x0002U) /* Serial data output value is "1" */
+/* Serial clock output of channel 0 (CKOm0) */
+#define _0000_SAU_CH0_CLOCK_OUTPUT_0             (0x0000U) /* Serial clock output value is "0" */
+#define _0100_SAU_CH0_CLOCK_OUTPUT_1             (0x0100U) /* Serial clock output value is "1" */
+/* Serial clock output of channel 1 (CKOm1) */
+#define _0000_SAU_CH1_CLOCK_OUTPUT_0             (0x0000U) /* Serial clock output value is "0" */
+#define _0200_SAU_CH1_CLOCK_OUTPUT_1             (0x0200U) /* Serial clock output value is "1" */
+
+/*
+    SAU Standby Control Register m (SSCm)
+*/
+/* SAU Standby Wakeup Control Bit (SWC) */
+#define _0000_SAU_CH0_SNOOZE_OFF                 (0x0000U) /* disable start function from STOP state of chip */
+#define _0001_SAU_CH0_SNOOZE_ON                  (0x0001U) /* enable start function from STOP state of chip */
+
+/*
+   Serial slave select enable register m (SSEmn)
+*/
+/* SAU0 Channel 0 SSI00 input setting in CSI communication and slave mode (SSE00) */
+#define _00_SAU_CH0_SSI00_UNUSED                 (0x00U)      /* disables SSI00 pin input */
+#define _01_SAU_CH0_SSI00_USED                   (0x01U)      /* enables SSI00 pin input */
+/* SAU0 Channel 1 SSI01 input setting in CSI communication and slave mode (SSE01) */
+#define _00_SAU_CH1_SSI01_UNUSED                 (0x00U)      /* disables SSI01 pin input */
+#define _02_SAU_CH1_SSI01_USED                   (0x02U)      /* enables SSI01 pin input */
+/* SAU1 Channel 0 SSI10 input setting in CSI communication and slave mode (SSE10) */
+#define _00_SAU_CH0_SSI10_UNUSED                 (0x00U)      /* disables SSI10 pin input */
+#define _01_SAU_CH0_SSI10_USED                   (0x01U)      /* enables SSI10 pin input */
+/* SAU1 Channel 1 SSI11 input setting in CSI communication and slave mode (SSE11) */
+#define _00_SAU_CH1_SSI11_UNUSED                 (0x00U)      /* disables SSI11 pin input */
+#define _02_SAU_CH1_SSI11_USED                   (0x02U)      /* enables SSI11 pin input */
+
+/* SAU used flag */
+#define _00_SAU_IIC_MASTER_FLAG_CLEAR            (0x00U)
+#define _01_SAU_IIC_SEND_FLAG                    (0x01U)
+#define _02_SAU_IIC_RECEIVE_FLAG                 (0x02U)
+#define _04_SAU_IIC_SENDED_ADDRESS_FLAG          (0x04U)
+
+
+/*
+    IICA Control Register (IICCTLn0)
+*/
+/* IIC operation enable (IICEn) */
+#define _00_IICA_OPERATION_DISABLE               (0x00U)   /* stop operation */
+#define _80_IICA_OPERATION_ENABLE                (0x80U)   /* enable operation */
+/* Exit from communications (LRELn) */
+#define _00_IICA_COMMUNICATION_NORMAL            (0x00U)   /* normal operation */
+#define _40_IICA_COMMUNICATION_EXIT              (0x40U)   /* exit from current communication */
+/* Wait cancellation (WRELn) */
+#define _00_IICA_WAIT_NOTCANCEL                  (0x00U)   /* do not cancel wait */
+#define _20_IICA_WAIT_CANCEL                     (0x20U)   /* cancel wait */
+/* Generation of interrupt when stop condition (SPIEn) */
+#define _00_IICA_STOPINT_DISABLE                 (0x00U)   /* disable */
+#define _10_IICA_STOPINT_ENABLE                  (0x10U)   /* enable */
+/* Wait and interrupt generation (WTIMn) */
+#define _00_IICA_WAITINT_CLK8FALLING             (0x00U)   /* generated at the eighth clock's falling edge */
+#define _08_IICA_WAITINT_CLK9FALLING             (0x08U)   /* generated at the ninth clock's falling edge */
+/* Acknowledgement control (ACKEn) */
+#define _00_IICA_ACK_DISABLE                     (0x00U)   /* disable acknowledgement */
+#define _04_IICA_ACK_ENABLE                      (0x04U)   /* enable acknowledgement */
+/* Start condition trigger (STTn) */
+#define _00_IICA_START_NOTGENERATE               (0x00U)   /* do not generate start condition */
+#define _02_IICA_START_GENERATE                  (0x02U)   /* generate start condition */
+/* Stop condition trigger (SPTn) */
+#define _00_IICA_STOP_NOTGENERATE                (0x00U)   /* do not generate stop condition */
+#define _01_IICA_STOP_GENERATE                   (0x01U)   /* generate stop condition */
+
+/*
+    IICA Status Register (IICSn)
+*/
+/* Master device status (MSTSn) */
+#define _00_IICA_STATUS_NOTMASTER                (0x00U)   /* slave device status or communication standby status */
+#define _80_IICA_STATUS_MASTER                   (0x80U)   /* master device communication status */
+/* Detection of arbitration loss (ALDn) */
+#define _00_IICA_ARBITRATION_NO                  (0x00U)   /* arbitration win or no arbitration */
+#define _40_IICA_ARBITRATION_LOSS                (0x40U)   /* arbitration loss */
+/* Detection of extension code reception (EXCn) */
+#define _00_IICA_EXTCODE_NOT                     (0x00U)   /* extension code not received */
+#define _20_IICA_EXTCODE_RECEIVED                (0x20U)   /* extension code received */
+/* Detection of matching addresses (COIn) */
+#define _00_IICA_ADDRESS_NOTMATCH                (0x00U)   /* addresses do not match */
+#define _10_IICA_ADDRESS_MATCH                   (0x10U)   /* addresses match */
+/* Detection of transmit/receive status (TRCn) */
+#define _00_IICA_STATUS_RECEIVE                  (0x00U)   /* receive status */ 
+#define _08_IICA_STATUS_TRANSMIT                 (0x08U)   /* transmit status */
+/* Detection of acknowledge signal (ACKDn) */
+#define _00_IICA_ACK_NOTDETECTED                 (0x00U)   /* ACK signal was not detected */
+#define _04_IICA_ACK_DETECTED                    (0x04U)   /* ACK signal was detected */
+/* Detection of start condition (STDn) */
+#define _00_IICA_START_NOTDETECTED               (0x00U)   /* start condition not detected */
+#define _02_IICA_START_DETECTED                  (0x02U)   /* start condition detected */
+/* Detection of stop condition (SPDn) */
+#define _00_IICA_STOP_NOTDETECTED                (0x00U)   /* stop condition not detected */
+#define _01_IICA_STOP_DETECTED                   (0x01U)   /* stop condition detected */
+
+/*
+    IICA Flag Register (IICFn)
+*/
+/* STT clear flag (STCFn) */
+#define _00_IICA_STARTFLAG_GENERATE              (0x00U)   /* generate start condition */
+#define _80_IICA_STARTFLAG_UNSUCCESSFUL          (0x80U)   /* start condition generation unsuccessful */
+/* IIC bus status flag (IICBSYn) */
+#define _00_IICA_BUS_RELEASE                     (0x00U)   /* bus release status */
+#define _40_IICA_BUS_COMMUNICATION               (0x40U)   /* bus communication status */
+/* Initial start enable trigger (STCENn) */
+#define _00_IICA_START_WITHSTOP                  (0x00U)   /* generate start upon detecting stop condition */
+#define _02_IICA_START_WITHOUTSTOP               (0x02U)   /* generate start without detecting stop condition */
+/* Communication reservation function disable bit (IICRSVn) */
+#define _00_IICA_RESERVATION_ENABLE              (0x00U)   /* enable communication reservation */
+#define _01_IICA_RESERVATION_DISABLE             (0x01U)   /* disable communication reservation */
+
+/*
+    IICA Control Register 1 (IICCTLn1)
+*/
+/* Control of address match wakeup (WUPn) */
+#define _00_IICA_WAKEUP_STOP                     (0x00U)   /* stop address match wakeup function in STOP mode */
+#define _80_IICA_WAKEUP_ENABLE                   (0x80U)   /* enable address match wakeup function in STOP mode */
+/* Detection of SCL0 pin level (CLDn) */
+#define _00_IICA_SCL_LOW                         (0x00U)   /* detect clock line at low level */
+#define _20_IICA_SCL_HIGH                        (0x20U)   /* detect clock line at high level */
+/* Detection of SDA0 pin level (DADn) */
+#define _00_IICA_SDA_LOW                         (0x00U)   /* detect data line at low level */
+#define _10_IICA_SDA_HIGH                        (0x10U)   /* detect data line at high level */
+/* Operation mode switching (SMCn) */
+#define _00_IICA_MODE_STANDARD                   (0x00U)   /* operates in standard mode */
+#define _08_IICA_MODE_HIGHSPEED                  (0x08U)   /* operates in high-speed mode */
+/* Digital filter operation control (DFCn) */
+#define _00_IICA_FILTER_OFF                      (0x00U)   /* digital filter off */ 
+#define _04_IICA_FILTER_ON                       (0x04U)   /* digital filter on */
+/* Operation of clock dividing frequency permission (PRSn) */
+#define _00_IICA_fCLK                            (0x00U)   /* clock of dividing frequency operation (fCLK) */ 
+#define _01_IICA_fCLK_HALF                       (0x01U)   /* 2 clock of dividing frequency operation (fCLK/2) */
+
+/* IICA used flag */
+#define _80_IICA_ADDRESS_COMPLETE                (0x80U)
+#define _00_IICA_MASTER_FLAG_CLEAR               (0x00U)
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+#define _8800_UART0_RECEIVE_DIVISOR              (0x8800U)
+#define _8800_UART0_TRANSMIT_DIVISOR             (0x8800U)
+#define _8800_UART1_RECEIVE_DIVISOR              (0x8800U)
+#define _8800_UART1_TRANSMIT_DIVISOR             (0x8800U)
+#define _10_IICA0_MASTERADDRESS                  (0x10U)
+#define _55_IICA0_IICWH_VALUE                    (0x55U)
+#define _4C_IICA0_IICWL_VALUE                    (0x4CU)
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+void R_SAU0_Create(void);
+void R_UART0_Create(void);
+void R_UART0_Start(void);
+void R_UART0_Stop(void);
+MD_STATUS R_UART0_Send(uint8_t * const tx_buf, uint16_t tx_num);
+MD_STATUS R_UART0_Receive(uint8_t * const rx_buf, uint16_t rx_num);
+static void r_uart0_callback_error(uint8_t err_type);
+static void r_uart0_callback_receiveend(void);
+static void r_uart0_callback_sendend(void);
+static void r_uart0_callback_softwareoverrun(uint16_t rx_data);
+void R_SAU1_Create(void);
+void R_UART1_Create(void);
+void R_UART1_Start(void);
+void R_UART1_Stop(void);
+MD_STATUS R_UART1_Send(uint8_t * const tx_buf, uint16_t tx_num);
+MD_STATUS R_UART1_Receive(uint8_t * const rx_buf, uint16_t rx_num);
+static void r_uart1_callback_error(uint8_t err_type);
+static void r_uart1_callback_receiveend(void);
+static void r_uart1_callback_sendend(void);
+static void r_uart1_callback_softwareoverrun(uint16_t rx_data);
+void R_IICA0_Create(void);
+MD_STATUS R_IICA0_Master_Send(uint8_t adr, uint8_t * const tx_buf, uint16_t tx_num, uint8_t wait);
+MD_STATUS R_IICA0_Master_Receive(uint8_t adr, uint8_t * const rx_buf, uint16_t rx_num, uint8_t wait);
+void R_IICA0_Stop(void);
+void R_IICA0_StopCondition(void);
+static void r_iica0_callback_master_sendend(void);
+static void r_iica0_callback_master_receiveend(void);
+static void r_iica0_callback_master_error(MD_STATUS flag);
+static void iica0_masterhandler(void);
+static void iica0_slavehandler(void);
+
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif

r_cg_serial_user.c

@@ -0,0 +1,545 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_serial_user.c
+* Version      : CodeGenerator for RL78/F14 V2.03.07.02 [08 Nov 2021]
+* Device(s)    : R5F10PPJ
+* Tool-Chain   : CCRL
+* Description  : This file implements device driver for Serial module.
+* Creation Date: 2026-08-03
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "r_cg_serial.h"
+/* Start user code for include. Do not edit comment generated here */
+#include "uart.h"
+#include "i2c.h"
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+#pragma interrupt r_uart0_interrupt_send(vect=INTST0)
+#pragma interrupt r_uart0_interrupt_receive(vect=INTSR0)
+#pragma interrupt r_uart1_interrupt_send(vect=INTST1)
+#pragma interrupt r_uart1_interrupt_receive(vect=INTSR1)
+#pragma interrupt r_iica0_interrupt(vect=INTIICA0)
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+extern volatile uint8_t * gp_uart0_tx_address;         /* uart0 send buffer address */
+extern volatile uint16_t  g_uart0_tx_count;            /* uart0 send data number */
+extern volatile uint8_t * gp_uart0_rx_address;         /* uart0 receive buffer address */
+extern volatile uint16_t  g_uart0_rx_count;            /* uart0 receive data number */
+extern volatile uint16_t  g_uart0_rx_length;           /* uart0 receive data length */
+extern volatile uint8_t * gp_uart1_tx_address;         /* uart1 send buffer address */
+extern volatile uint16_t  g_uart1_tx_count;            /* uart1 send data number */
+extern volatile uint8_t * gp_uart1_rx_address;         /* uart1 receive buffer address */
+extern volatile uint16_t  g_uart1_rx_count;            /* uart1 receive data number */
+extern volatile uint16_t  g_uart1_rx_length;           /* uart1 receive data length */
+extern volatile uint8_t   g_iica0_master_status_flag;  /* iica0 master flag */ 
+extern volatile uint8_t   g_iica0_slave_status_flag;   /* iica0 slave flag */
+extern volatile uint8_t * gp_iica0_rx_address;         /* iica0 receive buffer address */
+extern volatile uint16_t  g_iica0_rx_cnt;              /* iica0 receive data length */
+extern volatile uint16_t  g_iica0_rx_len;              /* iica0 receive data count */
+extern volatile uint8_t * gp_iica0_tx_address;         /* iica0 send buffer address */
+extern volatile uint16_t  g_iica0_tx_cnt;              /* iica0 send data count */
+/* Start user code for global. Do not edit comment generated here */
+extern volatile uint8_t  rs485_rx_done;
+extern volatile uint16_t  rs485_rx_index;
+extern volatile uint8_t  rs485_rx_buffer[UART_RX_BUF_SIZE];
+extern volatile uint16_t rs485_rx_length;
+extern volatile uint8_t g_rs485_bridge_active;
+extern volatile uint8_t g_rs485_bridge_done;
+void RS485_Bridge_Push(uint8_t b);
+
+extern volatile uint32_t g_uart0_err_fef;
+extern volatile uint32_t g_uart0_err_ovf;
+extern volatile uint32_t g_uart0_err_pef;
+extern volatile uint8_t g_rs485_need_recover;
+extern volatile uint8_t g_uart0_tx_done;
+extern volatile uint8_t g_uart1_tx_done;
+
+extern volatile uint16_t g_rs485_bridge_seq;
+
+
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+* Function Name: r_uart0_interrupt_receive
+* Description  : This function is INTSR0 interrupt service routine.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+static void __near r_uart0_interrupt_receive(void)
+{
+    volatile uint8_t rx_data;
+    volatile uint8_t err_type;
+    
+    err_type = (uint8_t)(SSR01 & 0x0007U);
+    SIR01 = (uint16_t)err_type;
+    
+    if (err_type != 0U)
+    {
+        r_uart0_callback_error(err_type);
+    }
+    
+    rx_data = SDR01L;
+
+    if (g_uart0_rx_length > g_uart0_rx_count)
+    {
+        *gp_uart0_rx_address = rx_data;
+        gp_uart0_rx_address++;
+        g_uart0_rx_count++;	
+
+        if (g_uart0_rx_length == g_uart0_rx_count)
+        {
+            r_uart0_callback_receiveend();
+        }
+    }
+    else
+    {
+        r_uart0_callback_softwareoverrun(rx_data);
+    }
+}
+
+/***********************************************************************************************************************
+* Function Name: r_uart0_interrupt_send
+* Description  : This function is INTST0 interrupt service routine.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+static void __near r_uart0_interrupt_send(void)
+{
+    if (g_uart0_tx_count > 0U)
+    {
+        SDR00L = *gp_uart0_tx_address;
+        gp_uart0_tx_address++;
+        g_uart0_tx_count--;
+    }
+    else
+    {
+        r_uart0_callback_sendend();
+    }
+}
+
+/***********************************************************************************************************************
+* Function Name: r_uart0_callback_receiveend
+* Description  : This function is a callback function when UART0 finishes reception.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+static void r_uart0_callback_receiveend(void)
+{
+    /* Start user code. Do not edit comment generated here */
+    uint8_t c = rs485_rx_buffer[rs485_rx_index];
+
+    if (g_rs485_bridge_active)
+    {
+        RS485_Bridge_Push(c);
+        g_rs485_bridge_seq++;
+        rs485_rx_index  = 0;
+        rs485_rx_length = 0;
+        R_UART0_Receive((uint8_t *)&rs485_rx_buffer[0], 1);
+        return;
+    }
+
+    if (rs485_rx_index < (UART_RX_BUF_SIZE - 1))
+    {
+        rs485_rx_index++;
+        rs485_rx_length = rs485_rx_index;
+    }
+    else
+    {
+        rs485_rx_done = 1;
+        return;
+    }
+
+    if (c == '\r')
+    {
+        R_UART0_Receive((uint8_t *)&rs485_rx_buffer[rs485_rx_index], 1);
+        return;
+    }
+
+    if (c == '\n')
+    {
+        rs485_rx_done = 1;
+        return;
+    }
+
+    R_UART0_Receive((uint8_t *)&rs485_rx_buffer[rs485_rx_index], 1);
+    /* End user code. Do not edit comment generated here */
+}
+
+/***********************************************************************************************************************
+* Function Name: r_uart0_callback_softwareoverrun
+* Description  : This function is a callback function when UART0 receives an overflow data.
+* Arguments    : rx_data -
+*                    receive data
+* Return Value : None
+***********************************************************************************************************************/
+static void r_uart0_callback_softwareoverrun(uint16_t rx_data)
+{
+    /* Start user code. Do not edit comment generated here */
+    /* End user code. Do not edit comment generated here */
+}
+
+/***********************************************************************************************************************
+* Function Name: r_uart0_callback_sendend
+* Description  : This function is a callback function when UART0 finishes transmission.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+static void r_uart0_callback_sendend(void)
+{
+    /* Start user code. Do not edit comment generated here */
+     rs485_set_tx(0);         
+    g_uart0_tx_done = 1;
+    /* End user code. Do not edit comment generated here */
+}
+
+/***********************************************************************************************************************
+* Function Name: r_uart0_callback_error
+* Description  : This function is a callback function when UART0 reception error occurs.
+* Arguments    : err_type -
+*                    error type value
+* Return Value : None
+***********************************************************************************************************************/
+static void r_uart0_callback_error(uint8_t err_type)
+{
+    /* Start user code. Do not edit comment generated here */
+    if (err_type & 0x04) g_uart0_err_fef++; // Framing
+    if (err_type & 0x01) g_uart0_err_ovf++; // Overrun
+    if (err_type & 0x02) g_uart0_err_pef++; // Parity
+    
+    (void)err_type;
+
+    // 1) ?? ?? ?? ??
+    rs485_rx_done   = 0;
+    rs485_rx_index  = 0;
+    rs485_rx_length = 0;
+    
+    g_rs485_need_recover = 1;
+    /* End user code. Do not edit comment generated here */
+}
+
+/***********************************************************************************************************************
+* Function Name: r_uart1_interrupt_receive
+* Description  : This function is INTSR1 interrupt service routine.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+static void __near r_uart1_interrupt_receive(void)
+{
+    volatile uint8_t rx_data;
+    volatile uint8_t err_type;
+    
+    err_type = (uint8_t)(SSR11 & 0x0007U);
+    SIR11 = (uint16_t)err_type;
+    
+    if (err_type != 0U)
+    {
+        r_uart1_callback_error(err_type);
+    }
+    
+    rx_data = SDR11L;
+
+    if (g_uart1_rx_length > g_uart1_rx_count)
+    {
+        *gp_uart1_rx_address = rx_data;
+        gp_uart1_rx_address++;
+        g_uart1_rx_count++;	
+
+        if (g_uart1_rx_length == g_uart1_rx_count)
+        {
+            r_uart1_callback_receiveend();
+        }
+    }
+    else
+    {
+        r_uart1_callback_softwareoverrun(rx_data);
+    }
+}
+
+/***********************************************************************************************************************
+* Function Name: r_uart1_interrupt_send
+* Description  : This function is INTST1 interrupt service routine.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+static void __near r_uart1_interrupt_send(void)
+{
+    if (g_uart1_tx_count > 0U)
+    {
+        SDR10L = *gp_uart1_tx_address;
+        gp_uart1_tx_address++;
+        g_uart1_tx_count--;
+    }
+    else
+    {
+        r_uart1_callback_sendend();
+    }
+}
+
+/***********************************************************************************************************************
+* Function Name: r_uart1_callback_receiveend
+* Description  : This function is a callback function when UART1 finishes reception.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+static void r_uart1_callback_receiveend(void)
+{
+    /* Start user code. Do not edit comment generated here */
+      /* ?? ???? uart_rx_buffer[uart_rx_index]? ??? ?? */
+    uint8_t c = uart_rx_buffer[uart_rx_index];
+
+    /* index ?? (? uint16_t? 255 ??? ??) */
+    if (uart_rx_index < (UART_RX_BUF_SIZE - 1)) {
+        uart_rx_index++;
+        uart_rx_length = uart_rx_index;
+    } else {
+        /* ?? ??: ???? ?? ?? */
+        uart_rx_done = 1;
+        return;
+    }
+
+    /* CR? ??(??? CRLF?? ?? ?? ??) */
+    if (c == '\r') {
+        R_UART1_Receive((uint8_t *)&uart_rx_buffer[uart_rx_index], 1);
+        return;
+    }
+
+    /* LF??? ?? ?? */
+    if (c == '\n') {
+        uart_rx_done = 1;
+        return;
+    }
+
+    /* ?? 1??? ?? ?? */
+    R_UART1_Receive((uint8_t *)&uart_rx_buffer[uart_rx_index], 1);
+    
+    /* End user code. Do not edit comment generated here */
+}
+
+/***********************************************************************************************************************
+* Function Name: r_uart1_callback_softwareoverrun
+* Description  : This function is a callback function when UART1 receives an overflow data.
+* Arguments    : rx_data -
+*                    receive data
+* Return Value : None
+***********************************************************************************************************************/
+static void r_uart1_callback_softwareoverrun(uint16_t rx_data)
+{
+    /* Start user code. Do not edit comment generated here */
+    /* End user code. Do not edit comment generated here */
+}
+
+/***********************************************************************************************************************
+* Function Name: r_uart1_callback_sendend
+* Description  : This function is a callback function when UART1 finishes transmission.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+static void r_uart1_callback_sendend(void)
+{
+    /* Start user code. Do not edit comment generated here */
+	g_uart1_tx_done = 1;
+    /* End user code. Do not edit comment generated here */
+}
+
+/***********************************************************************************************************************
+* Function Name: r_uart1_callback_error
+* Description  : This function is a callback function when UART1 reception error occurs.
+* Arguments    : err_type -
+*                    error type value
+* Return Value : None
+***********************************************************************************************************************/
+static void r_uart1_callback_error(uint8_t err_type)
+{
+    /* Start user code. Do not edit comment generated here */
+    /* End user code. Do not edit comment generated here */
+}
+
+/***********************************************************************************************************************
+* Function Name: r_iica0_interrupt
+* Description  : This function is INTIICA0 interrupt service routine.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+static void __near r_iica0_interrupt(void)
+{
+    if ((IICS0 & _80_IICA_STATUS_MASTER) == 0x80U)
+    {
+        iica0_masterhandler();
+    }
+}
+
+/***********************************************************************************************************************
+* Function Name: iica0_masterhandler
+* Description  : This function is IICA0 master handler.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+static void iica0_masterhandler(void)
+{
+    /* Detection of stop condition handling */
+    if ((0U == IICBSY0) && (g_iica0_tx_cnt != 0U))
+    {
+        r_iica0_callback_master_error(MD_SPT);
+    }
+    else
+    {
+        /* Control for sended address */
+        if ((g_iica0_master_status_flag & _80_IICA_ADDRESS_COMPLETE) == 0U)
+        {
+            if (1U == ACKD0)
+            {
+                g_iica0_master_status_flag |= _80_IICA_ADDRESS_COMPLETE;
+
+                if (1U == TRC0)
+                {
+                    WTIM0 = 1U;
+
+                    if (g_iica0_tx_cnt > 0U)
+                    {
+                        IICA0 = *gp_iica0_tx_address;
+                        gp_iica0_tx_address++;
+                        g_iica0_tx_cnt--;
+                    }
+                    else
+                    {
+                        r_iica0_callback_master_sendend();
+                    }
+                }
+                else
+                {
+                    ACKE0 = 1U;
+                    WTIM0 = 0U;
+                    WREL0 = 1U;
+                }
+            }
+            else
+            {
+                r_iica0_callback_master_error(MD_NACK);
+            }
+        }
+        else
+        {
+            /* Master send control */
+            if (1U == TRC0)
+            {
+                if ((0U == ACKD0) && (g_iica0_tx_cnt != 0U))
+                {
+                    r_iica0_callback_master_error(MD_NACK);
+                }
+                else
+                {
+                    if (g_iica0_tx_cnt > 0U)
+                    {
+                        IICA0 = *gp_iica0_tx_address;
+                        gp_iica0_tx_address++;
+                        g_iica0_tx_cnt--;
+                    }
+                    else
+                    {
+                        r_iica0_callback_master_sendend();
+                    }
+                }
+            }
+            /* Master receive control */
+            else
+            {
+                if (g_iica0_rx_cnt < g_iica0_rx_len)
+                {
+                    *gp_iica0_rx_address = IICA0;
+                    gp_iica0_rx_address++;
+                    g_iica0_rx_cnt++;
+
+                    if (g_iica0_rx_cnt == g_iica0_rx_len)
+                    {
+                        ACKE0 = 0U;
+                        WTIM0 = 1U;
+                        WREL0 = 1U;
+                    }
+                    else
+                    {
+                        WREL0 = 1U;
+                    }
+                }
+                else
+                {
+                    r_iica0_callback_master_receiveend();
+                }
+            }
+        }
+    }
+}
+
+/***********************************************************************************************************************
+* Function Name: r_iica0_callback_master_error
+* Description  : This function is a callback function when IICA0 master error occurs.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+static void r_iica0_callback_master_error(MD_STATUS flag)
+{
+    /* Start user code. Do not edit comment generated here */
+      i2c_rx_done = 1;
+    i2c_tx_done = 1;
+    /* End user code. Do not edit comment generated here */
+}
+
+/***********************************************************************************************************************
+* Function Name: r_iica0_callback_master_receiveend
+* Description  : This function is a callback function when IICA0 finishes master reception.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+static void r_iica0_callback_master_receiveend(void)
+{
+    SPT0 = 1U;
+    /* Start user code. Do not edit comment generated here */
+      i2c_rx_done = 1;
+    /* End user code. Do not edit comment generated here */
+}
+
+/***********************************************************************************************************************
+* Function Name: r_iica0_callback_master_sendend
+* Description  : This function is a callback function when IICA0 finishes master transmission.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+static void r_iica0_callback_master_sendend(void)
+{
+    SPT0 = 1U;
+    /* Start user code. Do not edit comment generated here */
+    i2c_tx_done = 1;
+    /* End user code. Do not edit comment generated here */
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */

r_cg_userdefine.h

@@ -0,0 +1,38 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_userdefine.h
+* Version      : CodeGenerator for RL78/F14 V2.03.07.02 [08 Nov 2021]
+* Device(s)    : R5F10PPJ
+* Tool-Chain   : CCRL
+* Description  : This file includes user definition.
+* Creation Date: 2026-08-03
+***********************************************************************************************************************/
+
+#ifndef _USER_DEF_H
+#define _USER_DEF_H
+
+/***********************************************************************************************************************
+User definitions
+***********************************************************************************************************************/
+
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif

r_cg_wdt.c

@@ -0,0 +1,74 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_wdt.c
+* Version      : CodeGenerator for RL78/F14 V2.03.07.02 [08 Nov 2021]
+* Device(s)    : R5F10PPJ
+* Tool-Chain   : CCRL
+* Description  : This file implements device driver for WDT module.
+* Creation Date: 2026-08-03
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "r_cg_wdt.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+* Function Name: R_WDT_Create
+* Description  : This function initializes the watchdogtimer.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_WDT_Create(void)
+{
+    WDTIMK = 1U;    /* disable INTWDTI interrupt */
+    WDTIIF = 0U;    /* clear INTWDTI interrupt flag */
+}
+
+/***********************************************************************************************************************
+* Function Name: R_WDT_Restart
+* Description  : This function restarts the watchdog timer.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_WDT_Restart(void)
+{
+    WDTE = 0xACU;     /* restart watchdog timer */
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */

r_cg_wdt.h

@@ -0,0 +1,52 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_wdt.h
+* Version      : CodeGenerator for RL78/F14 V2.03.07.02 [08 Nov 2021]
+* Device(s)    : R5F10PPJ
+* Tool-Chain   : CCRL
+* Description  : This file implements device driver for WDT module.
+* Creation Date: 2026-08-03
+***********************************************************************************************************************/
+
+#ifndef WDT_H
+#define WDT_H
+
+/***********************************************************************************************************************
+Macro definitions (Register bit)
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Macro definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Typedef definitions
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Global functions
+***********************************************************************************************************************/
+void R_WDT_Create(void);
+void R_WDT_Restart(void);
+
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif

r_cg_wdt_user.c

@@ -0,0 +1,51 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_cg_wdt_user.c
+* Version      : CodeGenerator for RL78/F14 V2.03.07.02 [08 Nov 2021]
+* Device(s)    : R5F10PPJ
+* Tool-Chain   : CCRL
+* Description  : This file implements device driver for WDT module.
+* Creation Date: 2026-08-03
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "r_cg_wdt.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */

r_systeminit.c

@@ -0,0 +1,97 @@
+/***********************************************************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
+* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+* applicable laws, including copyright laws. 
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
+* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
+* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
+* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
+* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
+* of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
+* following link:
+* http://www.renesas.com/disclaimer
+*
+* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved.
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+* File Name    : r_systeminit.c
+* Version      : CodeGenerator for RL78/F14 V2.03.07.02 [08 Nov 2021]
+* Device(s)    : R5F10PPJ
+* Tool-Chain   : CCRL
+* Description  : This file implements system initializing function.
+* Creation Date: 2026-08-03
+***********************************************************************************************************************/
+
+/***********************************************************************************************************************
+Includes
+***********************************************************************************************************************/
+#include "r_cg_macrodriver.h"
+#include "r_cg_cgc.h"
+#include "r_cg_port.h"
+#include "r_cg_serial.h"
+#include "r_cg_wdt.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "r_cg_userdefine.h"
+
+/***********************************************************************************************************************
+Pragma directive
+***********************************************************************************************************************/
+/* Start user code for pragma. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+Global variables and functions
+***********************************************************************************************************************/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/***********************************************************************************************************************
+* Function Name: R_Systeminit
+* Description  : This function initializes every macro.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void R_Systeminit(void)
+{
+    /* Set periperal I/O redirection */
+    PIOR0 = 0x00U;
+    PIOR1 = 0x00U;
+    PIOR2 = 0x00U;
+    PIOR3 = 0x00U;
+    PIOR4 = 0x00U;
+    PIOR5 = 0x00U;
+    PIOR6 = 0x00U;
+    PIOR7 = 0x00U;
+    PIOR8 = 0x00U;
+    R_CGC_Get_ResetSource();
+    R_CGC_Create();
+    R_PORT_Create();
+    R_SAU0_Create();
+    R_SAU1_Create();
+    R_IICA0_Create();
+    R_WDT_Create();
+
+    /* Set invalid memory access detection control */
+    IAWCTL = 0x00U;
+}
+
+
+/***********************************************************************************************************************
+* Function Name: hdwinit
+* Description  : This function initializes hardware setting.
+* Arguments    : None
+* Return Value : None
+***********************************************************************************************************************/
+void hdwinit(void)
+{
+    DI();
+    R_Systeminit();
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */

stkinit.asm

@@ -0,0 +1,77 @@
+;/**********************************************************************************************************************
+; * DISCLAIMER
+; * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
+; * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
+; * applicable laws, including copyright laws.
+; * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+; * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
+; * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
+; * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
+; * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
+; * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+; * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
+; * this software. By using this software, you agree to the additional terms and conditions found by accessing the
+; * following link:
+; * http://www.renesas.com/disclaimer
+; *
+; * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
+; *********************************************************************************************************************/;---------------------------------------------------------------------
+;	_stkinit
+;
+;	void _stkinit(void __near * stackbss);
+;
+;	input:
+;		stackbss = AX (#LOWW(_stackend))
+;	output:
+;		NONE
+;---------------------------------------------------------------------
+
+;   NOTE       : THIS IS A TYPICAL EXAMPLE.
+
+	.PUBLIC	_stkinit
+
+.textf	.CSEG	TEXTF
+_stkinit:
+	MOVW	HL,AX		; stack_end_addr
+	MOV	[SP+3],#0x00	; [SP+0]-[SP+2] for return address
+	MOVW	AX,SP
+	SUBW	AX,HL		; SUBW  AX,#LOWW _@STEND
+	BNH	$LSTINIT3	; goto end
+	SHRW	AX,5		; loop count for 32 byte transfer
+	MOVW	BC,AX
+	CLRW	AX
+LSTINIT1:
+	CMPW	AX,BC
+	BZ	$LSTINIT2
+	MOVW	[HL],AX
+	MOVW	[HL+2],AX
+	MOVW	[HL+4],AX
+	MOVW	[HL+6],AX
+	MOVW	[HL+8],AX
+	MOVW	[HL+10],AX
+	MOVW	[HL+12],AX
+	MOVW	[HL+14],AX
+	MOVW	[HL+16],AX
+	MOVW	[HL+18],AX
+	MOVW	[HL+20],AX
+	MOVW	[HL+22],AX
+	MOVW	[HL+24],AX
+	MOVW	[HL+26],AX
+	MOVW	[HL+28],AX
+	MOVW	[HL+30],AX
+	XCHW	AX,HL
+	ADDW	AX,#0x20
+	XCHW	AX,HL
+	DECW	BC
+	BR	$LSTINIT1
+LSTINIT2:
+	MOVW	AX,SP
+	CMPW	AX,HL
+	BZ	$LSTINIT3	; goto end
+	CLRW	AX
+	MOVW	[HL],AX
+	INCW	HL
+	INCW	HL
+	BR	$LSTINIT2
+LSTINIT3:
+	RET

uart.c

@@ -0,0 +1,250 @@
+#include "uart.h"
+#include "delay.h"
+#include "r_cg_adc.h"
+#include "r_cg_port.h"
+#include <string.h>
+
+#define RS485_EN_PORT   P4
+#define RS485_EN_PM     PM4
+#define RS485_EN_MASK   (0x20U)   // P4.5
+
+volatile uint8_t g_uart0_tx_done = 1;
+volatile uint8_t g_uart1_tx_done = 1;
+extern volatile uint16_t g_uart1_tx_count;
+
+extern volatile uint8_t  rs485_rx_done;
+extern volatile uint16_t  rs485_rx_index;
+extern volatile uint16_t rs485_rx_length;
+extern volatile uint8_t  rs485_rx_buffer[];
+
+extern volatile uint8_t g_rs485_bridge_active;
+extern volatile uint8_t g_rs485_bridge_done;
+
+volatile uint8_t g_rs485_need_recover = 0;
+
+
+void rs485_recover(void)
+{
+     DI();               // ISR 경쟁 줄이기
+    rs485_set_tx(0);    // RX 모드 고정
+
+    // UART0 재시작
+    R_UART0_Stop();
+    delay_us(200);
+
+    R_UART0_Create();
+    delay_us(200);
+
+    R_UART0_Start();
+    delay_us(200);
+
+    // 에러 플래그/카운터 정리
+    g_uart0_err_fef = 0;
+    g_uart0_err_ovf = 0;
+    g_uart0_err_pef = 0;
+
+    // RX 다시 arm
+    rs485_rx_done   = 0;
+    rs485_rx_index  = 0;
+    rs485_rx_length = 0;
+    R_UART0_Receive((uint8_t*)&rs485_rx_buffer[0], 1);
+
+    g_rs485_need_recover = 0; 
+    EI();
+}
+
+
+/* UART1 송신용 내부 버퍼(스택 포인터 안전) */
+static uint8_t s_uart1_txbuf[1024];
+/* 129 data bytes as HEX plus diagnostics/CRLF. */
+static uint8_t s_uart0_txbuf[320];
+static volatile uint16_t s_uart0_tx_len = 0;
+                                  
+				  
+static void UART1_WaitTxIdle(void)
+{
+    unsigned long guard = 0;
+    while (g_uart1_tx_count != 0U) {
+        if (guard++ > 3000000UL) break;  // 무한루프 방지
+    }
+}
+				  
+
+void rs485_set_tx(uint8_t on)
+{
+    if (on) RS485_EN_PORT |= RS485_EN_MASK;      // EN=1 (TX)
+    else    RS485_EN_PORT &= (uint8_t)~RS485_EN_MASK; // EN=0 (RX)
+}
+
+void rs485_init(void)
+{
+    RS485_EN_PM &= (uint8_t)~RS485_EN_MASK;  // 출력
+    rs485_set_tx(0);                         // 기본 RX 모드
+}
+
+void UART0_WaitTxDone_Us(uint32_t timeout_us)
+{
+    while (!g_uart0_tx_done && timeout_us >= 10U) {
+        delay_us(10);
+        timeout_us -= 10U;
+    }
+}
+
+void RS485_Send(const uint8_t* data, uint16_t len)
+{
+    if (!data || len == 0) return;
+
+    /* 이전 전송 완료 대기 */
+    UART0_WaitTxDone_Us(UART0_TX_TIMEOUT_US);
+    if (!g_uart0_tx_done) {
+        g_rs485_need_recover = 1;
+        return;
+    }
+
+    /* 내부 버퍼 크기 제한 */
+    if (len >= (uint16_t)sizeof(s_uart0_txbuf)) {
+        len = (uint16_t)(sizeof(s_uart0_txbuf) - 1);
+    }
+
+    /* 호출자 버퍼 -> 내부 안전 버퍼 복사 */
+    memcpy(s_uart0_txbuf, data, len);
+    s_uart0_tx_len = len;
+
+    g_uart0_tx_done = 0;
+    rs485_set_tx(1);
+    delay_us(30U);
+
+    /* 내부 버퍼 기준 비동기 송신 */
+    R_UART0_Send((uint8_t*)s_uart0_txbuf, len);
+}
+
+void RS485_SendString(const char* s)
+{
+    uint16_t len = 0;
+    while (s[len] != '\0') len++;
+    RS485_Send((const uint8_t*)s, len);
+}
+
+static void UART1_WaitTxDone_Us(uint32_t timeout_us)
+{
+    while (!g_uart1_tx_done && timeout_us >= 10U) {
+        delay_us(10);
+        timeout_us -= 10U;
+    }
+}
+
+/**
+ * 함수명: uart_send_string
+ * 목적: null 종료된 문자열을 UART0로 전송
+ *
+ * 매개변수:
+ *   - str : 전송할 문자열 (C 문자열, '\0'로 종료)
+ *
+ * 반환값: 없음 (void)
+ *
+ * 동작 방식:
+ *   1) 문자열 길이 계산
+ *      - 문자열 끝을 나타내는 '\0'이 나올 때까지 len 증가
+ *
+ *   2) UART 전송
+ *      - R_UART0_Send() 함수를 사용하여 계산한 길이만큼 문자열 전송
+ *      - (uint8_t *)로 캐스팅하여 바이트 배열 형식 전달
+ *
+ * 참고:
+ *   - null 문자('\0')는 전송되지 않음
+ *   - UART0 초기화와 전송 준비는 별도로 되어 있어야 함
+ */
+ 
+ // UART0(RS485)
+void uart_send_string(const char *str)
+{
+    uint16_t len = 0;
+    while (str[len] != '\0') len++;
+
+    RS485_Send((const uint8_t*)str, len);
+}
+
+// UART1(PC)
+void uart1_send_string(const char *str)
+{
+    uint16_t len = 0;
+
+    if (str == 0) return;
+    while (str[len] != '\0') len++;
+
+    /* 이전 전송 끝날 때까지 대기 */
+    UART1_WaitTxIdle();
+    
+    g_uart1_tx_done = 0; 
+
+    /* 스택 포인터/버퍼 수명 문제 방지: 내부 버퍼로 복사 */
+    if (len >= (uint16_t)sizeof(s_uart1_txbuf))
+        len = (uint16_t)(sizeof(s_uart1_txbuf) - 1);
+
+    memcpy(s_uart1_txbuf, str, len);
+
+    /* 비동기 송신 시작 */
+    R_UART1_Send(s_uart1_txbuf, len);
+
+    /* 여기서 또 기다리지 말고(속도 저하). 다음 호출이 알아서 대기함 */
+}
+/**
+ * 함수명: uart_send_hex
+ * 목적: 8비트 값(uint8_t)을 16진수 문자열로 변환 후 UART0로 전송
+ *
+ * 매개변수:
+ *   - val : 전송할 8비트 값
+ *
+ * 반환값: 없음 (void)
+ *
+ * 동작 방식:
+ *   1) 상위/하위 4비트 분리
+ *      - high = val >> 4, 상위 4비트
+ *      - low  = val & 0x0F, 하위 4비트
+ *
+ *   2) 16진수 문자로 변환
+ *      - 0~9 → '0'~'9'
+ *      - 10~15 → 'A'~'F'
+ *      - hex[0] = 상위 4비트 문자
+ *      - hex[1] = 하위 4비트 문자
+ *
+ *   3) UART 전송
+ *      - R_UART0_Send()를 사용해 2바이트 전송
+ *
+ *   4) 전송 후 지연
+ *      - delay(10000)으로 약간의 전송 간격 확보
+ *
+ * 참고:
+ *   - 이 함수는 1바이트 값을 항상 2자리 16진수로 표현
+ *   - 예: val = 0xAF → "AF" 전송
+ */
+void uart_send_hex(uint8_t val)
+{
+    uint8_t hex[2];
+    uint8_t high = (val >> 4) & 0x0F;
+    uint8_t low = val & 0x0F;
+
+    hex[0] = (high < 10) ? ('0' + high) : ('A' + (high - 10));
+    hex[1] = (low < 10) ? ('0' + low) : ('A' + (low - 10));
+    
+    RS485_Send(hex, 2);
+    
+}
+
+void uart1_send_hex(uint8_t val)
+{
+    static uint8_t hex[2];
+    uint8_t high = (val >> 4) & 0x0F;
+    uint8_t low  = val & 0x0F;
+
+    hex[0] = (high < 10) ? ('0' + high) : ('A' + (high - 10));
+    hex[1] = (low  < 10) ? ('0' + low ) : ('A' + (low  - 10));
+
+    UART1_WaitTxIdle();
+    
+    g_uart1_tx_done = 0;
+    R_UART1_Send(hex, 2);
+}
+
+
+

uart.h

@@ -0,0 +1,68 @@
+#include "r_cg_macrodriver.h"
+#include "r_cg_serial.h"
+#include "r_cg_adc.h"
+
+
+
+#pragma once
+#include <stdint.h>
+
+extern volatile uint8_t g_uart0_tx_done;
+void UART0_WaitTxDone_Us(uint32_t timeout_us);
+
+/* 115200 bps, 8N1: the 319-byte UART0 TX buffer needs about 27.7 ms. */
+#define UART0_TX_TIMEOUT_US 40000UL
+
+#define ADC_RESOLUTION 1023.0f   // 10-bit ADC
+#define VREF           5.06f     // V
+#define RAM_BYTES      13             
+#define UART_RX_BUF_SIZE 1024
+
+extern volatile uint32_t g_uart0_err_fef;
+extern volatile uint32_t g_uart0_err_ovf;
+extern volatile uint32_t g_uart0_err_pef;
+
+// PC(USB, UART1) 출력 전용
+#define PC_PRINT(s)      uart1_send_string((s))
+#define PC_PRINT_HEX(v)  uart1_send_hex((v))
+
+// RS485(UART0) 출력/송신 전용
+#define RS485_PRINT(s)      uart_send_string((s))
+#define RS485_PRINT_HEX(v)  uart_send_hex((v))
+
+extern volatile uint8_t  uart_rx_done;
+extern volatile uint16_t  uart_rx_index;
+extern volatile uint8_t  uart_rx_buffer[UART_RX_BUF_SIZE];
+extern volatile uint16_t uart_rx_length;
+
+extern volatile uint8_t g_rs485_need_recover;
+
+extern volatile uint32_t g_uart0_err_fef;
+extern volatile uint32_t g_uart0_err_ovf;
+extern volatile uint32_t g_uart0_err_pef;
+
+extern uint8_t g_fixed_addr;
+
+#define HOST_PRINT(s) do {                 \
+    if (g_fixed_addr == 0) PC_PRINT(s);    \
+    else RS485_PRINT(s);                   \
+} while(0)
+
+void uart_send_string(const char *str);	// UART0(RS485)
+void uart_send_hex(uint8_t val);	// UART0(RS485)
+
+void uart1_send_string(const char *str);  // UART1(PC)
+void uart1_send_hex(uint8_t val);	  // UART1(PC)
+
+//void UART0_ReceiveHandler(void);
+void ADC_ReadAndSend_UART(void);
+void cmd_enter_command_mode(const unsigned char *d, unsigned int len);
+void cmd_unknown(const unsigned char *d, unsigned int len);
+
+// RS485 EN(P45)
+void rs485_init(void);
+void rs485_set_tx(uint8_t on);
+
+
+void rs485_recover(void);
+