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modify gatectrl

master
gudae 2 months ago
parent
bb5b0886af
commit
4ee2e168df
6 changed files with 142 additions and 145 deletions
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  1. BIN
      DefaultBuild/gatectrl.obj
  2. BIN
      DefaultBuild/multical.abs
  3. 2
      DefaultBuild/multical.map
  4. 54
      DefaultBuild/multical.mot
  5. 127
      gatectrl.c
  6. 104
      multical.temp.mtud

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@ -1,4 +1,4 @@
Renesas Optimizing Linker (W3.07.00 ) 26-Feb-2026 15:07:50 Renesas Optimizing Linker (W3.07.00 ) 27-Feb-2026 11:29:14
*** Options *** *** Options ***

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127
gatectrl.c
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@ -1,5 +1,4 @@
#include "gatectrl.h" #include "gatectrl.h"
static uint8_t s_ch = 1; static uint8_t s_ch = 1;
#define PORT_BIT_SETCLR(PORT, MASK, ON) \ #define PORT_BIT_SETCLR(PORT, MASK, ON) \
@ -7,7 +6,6 @@ static uint8_t s_ch = 1;
if (ON) { (PORT) |= (uint8_t)(MASK); } \ if (ON) { (PORT) |= (uint8_t)(MASK); } \
else { (PORT) &= (uint8_t)~(MASK); } \ else { (PORT) &= (uint8_t)~(MASK); } \
} while (0) } while (0)
void Gate_SetByNum(uint8_t ch, uint8_t hash_on, uint8_t anaout_on, uint8_t check_on) void Gate_SetByNum(uint8_t ch, uint8_t hash_on, uint8_t anaout_on, uint8_t check_on)
{ {
switch (ch) switch (ch)
@ -57,7 +55,7 @@ void Gate_SetByNum(uint8_t ch, uint8_t hash_on, uint8_t anaout_on, uint8_t check
case 8: /* P12.6, P4.1, P7.0 */ case 8: /* P12.6, P4.1, P7.0 */
PORT_BIT_SETCLR(P12, 0x40, hash_on); // P12.6 PORT_BIT_SETCLR(P12, 0x40, hash_on); // P12.6
PORT_BIT_SETCLR(P4, 0x02, anaout_on); // P4.1 PORT_BIT_SETCLR(P4, 0x02, anaout_on); // P4.1
PORT_BIT_SETCLR(P4, 0x40, check_on); // P7.0 -> p4.6으로 변경 PORT_BIT_SETCLR(P4, 0x40, check_on); // P7.0 -> p4.6???? ????
break; break;
case 9: /* P12.7, P5.0, P7.1 */ case 9: /* P12.7, P5.0, P7.1 */
@ -72,65 +70,66 @@ void Gate_SetByNum(uint8_t ch, uint8_t hash_on, uint8_t anaout_on, uint8_t check
PORT_BIT_SETCLR(P10, 0x10, check_on); // P10.4 PORT_BIT_SETCLR(P10, 0x10, check_on); // P10.4
break; break;
case 11: /* P10.3, P5.2, P10.5 */ case 11: /* P9.2, P13.0, P1.4 */
PORT_BIT_SETCLR(P10, 0x08, hash_on); // P10.3 PORT_BIT_SETCLR(P9, 0x04, hash_on); // P9.2
PORT_BIT_SETCLR(P5, 0x04, anaout_on); // P5.2 PORT_BIT_SETCLR(P13, 0x01, anaout_on); // P13.0
PORT_BIT_SETCLR(P10, 0x20, check_on); // P10.5 PORT_BIT_SETCLR(P1, 0x10, check_on); // P1.4
break; break;
case 12: /* P10.2, P6.0, P10.6 */ case 12: /* P9.3, P7.7, P1.3 */
PORT_BIT_SETCLR(P10, 0x04, hash_on); // P10.2 PORT_BIT_SETCLR(P9, 0x08, hash_on); // P9.3
PORT_BIT_SETCLR(P6, 0x01, anaout_on); // P6.0 PORT_BIT_SETCLR(P7, 0x80, anaout_on); // P7.7
PORT_BIT_SETCLR(P10, 0x40, check_on); // P10.6 PORT_BIT_SETCLR(P1, 0x08, check_on); // P1.3
break; break;
case 13: /* P10.1, P6.1, P10.7 */ case 13: /* P9.4, P7.6, P1.0 */
PORT_BIT_SETCLR(P10, 0x02, hash_on); // P10.1 PORT_BIT_SETCLR(P9, 0x10, hash_on); // P9.4
PORT_BIT_SETCLR(P6, 0x02, anaout_on); // P6.1 PORT_BIT_SETCLR(P7, 0x40, anaout_on); // P7.6
PORT_BIT_SETCLR(P10, 0x80, check_on); // P10.7 PORT_BIT_SETCLR(P1, 0x01, check_on); // P1.0
break; break;
case 14: /* P10.0, P7.2, P5.7 */ case 14: /* P9.5, P7.4, P5.4 */
PORT_BIT_SETCLR(P10, 0x01, hash_on); // P10.0 PORT_BIT_SETCLR(P9, 0x20, hash_on); // P9.5
PORT_BIT_SETCLR(P7, 0x04, anaout_on); // P7.2 PORT_BIT_SETCLR(P7, 0x10, anaout_on); // P7.4
PORT_BIT_SETCLR(P5, 0x80, check_on); // P5.7 PORT_BIT_SETCLR(P5, 0x10, check_on); // P5.4
break; break;
case 15: /* P9.7, P7.3, P5.6 */ case 15: /* P9.6, P7.5, P5.5 */
PORT_BIT_SETCLR(P9, 0x80, hash_on); // P9.7 PORT_BIT_SETCLR(P9, 0x40, hash_on); // P9.6
PORT_BIT_SETCLR(P7, 0x08, anaout_on); // P7.3 PORT_BIT_SETCLR(P7, 0x20, anaout_on); // P7.5
PORT_BIT_SETCLR(P5, 0x40, check_on); // P5.6 PORT_BIT_SETCLR(P5, 0x20, check_on); // P5.5
break; break;
case 16: /* P9.6, P7.5, P5.5 */ case 16: /* P9.7, P7.3, P5.6 */
PORT_BIT_SETCLR(P9, 0x40, hash_on); // P9.6 PORT_BIT_SETCLR(P9, 0x80, hash_on); // P9.7
PORT_BIT_SETCLR(P7, 0x20, anaout_on); // P7.5 PORT_BIT_SETCLR(P7, 0x08, anaout_on); // P7.3
PORT_BIT_SETCLR(P5, 0x20, check_on); // P5.5 PORT_BIT_SETCLR(P5, 0x40, check_on); // P5.6
break; break;
case 17: /* P9.5, P7.4, P5.4 */ case 17: /* P10.0, P7.2, P5.7 */
PORT_BIT_SETCLR(P9, 0x20, hash_on); // P9.5 PORT_BIT_SETCLR(P10, 0x01, hash_on); // P10.0
PORT_BIT_SETCLR(P7, 0x10, anaout_on); // P7.4 PORT_BIT_SETCLR(P7, 0x04, anaout_on); // P7.2
PORT_BIT_SETCLR(P5, 0x10, check_on); // P5.4 PORT_BIT_SETCLR(P5, 0x80, check_on); // P5.7
break; break;
case 18: /* P10.1, P6.1, P10.7 */
PORT_BIT_SETCLR(P10, 0x02, hash_on); // P10.1
PORT_BIT_SETCLR(P6, 0x02, anaout_on); // P6.1
PORT_BIT_SETCLR(P10, 0x80, check_on); // P10.7
break;
case 19: /* P10.2, P6.0, P10.6 */
PORT_BIT_SETCLR(P10, 0x04, hash_on); // P10.2
PORT_BIT_SETCLR(P6, 0x01, anaout_on); // P6.0
PORT_BIT_SETCLR(P10, 0x40, check_on); // P10.6
break;
case 20: /* P10.3, P5.2, P10.5 */
PORT_BIT_SETCLR(P10, 0x08, hash_on); // P10.3
PORT_BIT_SETCLR(P5, 0x04, anaout_on); // P5.2
PORT_BIT_SETCLR(P10, 0x20, check_on); // P10.5
break;
case 18: /* P9.4, P7.6, P1.0 */
PORT_BIT_SETCLR(P9, 0x10, hash_on); // P9.4
PORT_BIT_SETCLR(P7, 0x40, anaout_on); // P7.6
PORT_BIT_SETCLR(P1, 0x01, check_on); // P1.0
break;
case 19: /* P9.3, P7.7, P1.3 */
PORT_BIT_SETCLR(P9, 0x08, hash_on); // P9.3
PORT_BIT_SETCLR(P7, 0x80, anaout_on); // P7.7
PORT_BIT_SETCLR(P1, 0x08, check_on); // P1.3
break;
case 20: /* P9.2, P13.0, P1.4 */
PORT_BIT_SETCLR(P9, 0x04, hash_on); // P9.2
PORT_BIT_SETCLR(P13, 0x01, anaout_on); // P13.0
PORT_BIT_SETCLR(P1, 0x10, check_on); // P1.4
break;
default: default:
break; break;
@ -141,7 +140,7 @@ void Cal_Init(void)
{ {
uint8_t i; uint8_t i;
// P4.7 = 0, P15.7 = 1 (다른 비트 보존!) // P4.7 = 0, P15.7 = 1 (??? ??? ????!)
PORT_BIT_SETCLR(P4, 0x80, 0); PORT_BIT_SETCLR(P4, 0x80, 0);
PORT_BIT_SETCLR(P15, 0x80, 1); PORT_BIT_SETCLR(P15, 0x80, 1);
@ -154,7 +153,7 @@ void Eol_Init(void)
{ {
uint8_t i; uint8_t i;
// P4.7 = 1, P15.7 = 0 (다른 비트 보존!) // P4.7 = 1, P15.7 = 0 (??? ??? ????!)
PORT_BIT_SETCLR(P4, 0x80, 1); PORT_BIT_SETCLR(P4, 0x80, 1);
PORT_BIT_SETCLR(P15, 0x80, 1); PORT_BIT_SETCLR(P15, 0x80, 1);
@ -168,5 +167,3 @@ void GateCtrl_SelectChannel(uint8_t ch)
if (ch < 1 || ch > 20) return; if (ch < 1 || ch > 20) return;
s_ch = ch; s_ch = ch;
} }

104
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