gatectrl

DefaultBuild/multical.map

@@ -1,8 +1,4 @@
-<<<<<<< HEAD
-Renesas Optimizing Linker (W3.07.00 )             27-Feb-2026 16:00:59
-=======
-Renesas Optimizing Linker (W3.07.00 )             27-Feb-2026 11:29:14
->>>>>>> 4ee2e168dfece858fa5192b727334dcae342c7db
+Renesas Optimizing Linker (W3.07.00 )             03-Mar-2026 08:44:49
 
 *** Options ***
 

DefaultBuild/multical.mot

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-S1132E3201EF035A06FE8803D1DD056A0A40EF2C2E
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-S1132E6203D1DD056A0A20EF035A0ADF1004D7C72B
-S1132E725A047F6A0F80E1EF0C8800320001F0FEF1
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-S1132E92C76A04806A0F80E1EF0C8800320001F0F7
-S1132EA2FE5AFC8800819800318E441500DCEBC088
-S1132EB2D773D1DD0B318E441500DE04639FFAE330
-S1042EC2D734
->>>>>>> 4ee2e168dfece858fa5192b727334dcae342c7db
 S11330003C656E643E0D0A000D0A00556E6B6E6FD2
 S1133010776E20636D640D0A004572723A616464D0
 S1133020725F72616E67650D0A004572723A61647F

gatectrl.c

@@ -55,11 +55,8 @@ void Gate_SetByNum(uint8_t ch, uint8_t hash_on, uint8_t anaout_on, uint8_t check
         case 8: /* P12.6, P4.1, P7.0 */
             PORT_BIT_SETCLR(P12, 0x40, hash_on);    // P12.6
             PORT_BIT_SETCLR(P4,  0x02, anaout_on);  // P4.1
-<<<<<<< HEAD
             PORT_BIT_SETCLR(P4,  0x40, check_on);   // P7.0 -> p4.6         
-=======
-            PORT_BIT_SETCLR(P4,  0x40, check_on);   // P7.0 -> p4.6???? ????
->>>>>>> 4ee2e168dfece858fa5192b727334dcae342c7db
+
             break;
 
         case 9: /* P12.7, P5.0, P7.1 */
@@ -74,7 +71,6 @@ void Gate_SetByNum(uint8_t ch, uint8_t hash_on, uint8_t anaout_on, uint8_t check
             PORT_BIT_SETCLR(P10, 0x10, check_on);   // P10.4
             break;
 
-<<<<<<< HEAD
 	case 11: /* P9.2, P13.0, P1.4 */
 	    PORT_BIT_SETCLR(P9,  0x04, hash_on);    // P9.2
 	    PORT_BIT_SETCLR(P13, 0x01, anaout_on);  // P13.0
@@ -133,66 +129,6 @@ void Gate_SetByNum(uint8_t ch, uint8_t hash_on, uint8_t anaout_on, uint8_t check
 	    PORT_BIT_SETCLR(P10, 0x08, hash_on);    // P10.3
 	    PORT_BIT_SETCLR(P5,  0x04, anaout_on);  // P5.2
 	    PORT_BIT_SETCLR(P10, 0x20, check_on);   // P10.5
-=======
-	case 11: /* P9.2, P13.0, P1.4 */
-	    PORT_BIT_SETCLR(P9,  0x04, hash_on);    // P9.2
-	    PORT_BIT_SETCLR(P13, 0x01, anaout_on);  // P13.0
-	    PORT_BIT_SETCLR(P1,  0x10, check_on);   // P1.4
-	    break;
-
-	case 12: /* P9.3, P7.7, P1.3 */
-	    PORT_BIT_SETCLR(P9,  0x08, hash_on);    // P9.3
-	    PORT_BIT_SETCLR(P7,  0x80, anaout_on);  // P7.7
-	    PORT_BIT_SETCLR(P1,  0x08, check_on);   // P1.3
-	    break;
-
-	case 13: /* P9.4, P7.6, P1.0 */
-	    PORT_BIT_SETCLR(P9,  0x10, hash_on);    // P9.4
-	    PORT_BIT_SETCLR(P7,  0x40, anaout_on);  // P7.6
-	    PORT_BIT_SETCLR(P1,  0x01, check_on);   // P1.0
-	    break;
-
-	case 14: /* P9.5, P7.4, P5.4 */
-	    PORT_BIT_SETCLR(P9,  0x20, hash_on);    // P9.5
-	    PORT_BIT_SETCLR(P7,  0x10, anaout_on);  // P7.4
-	    PORT_BIT_SETCLR(P5,  0x10, check_on);   // P5.4
-	    break;
-
-	case 15: /* P9.6, P7.5, P5.5 */
-	    PORT_BIT_SETCLR(P9,  0x40, hash_on);    // P9.6
-	    PORT_BIT_SETCLR(P7,  0x20, anaout_on);  // P7.5
-	    PORT_BIT_SETCLR(P5,  0x20, check_on);   // P5.5
-	    break;
-
-	case 16: /* P9.7, P7.3, P5.6 */
-	    PORT_BIT_SETCLR(P9,  0x80, hash_on);    // P9.7
-	    PORT_BIT_SETCLR(P7,  0x08, anaout_on);  // P7.3
-	    PORT_BIT_SETCLR(P5,  0x40, check_on);   // P5.6
-	    break;
-
-	case 17: /* P10.0, P7.2, P5.7 */
-	    PORT_BIT_SETCLR(P10, 0x01, hash_on);    // P10.0
-	    PORT_BIT_SETCLR(P7,  0x04, anaout_on);  // P7.2
-	    PORT_BIT_SETCLR(P5,  0x80, check_on);   // P5.7
-	    break;
-
-	case 18: /* P10.1, P6.1, P10.7 */
-	    PORT_BIT_SETCLR(P10, 0x02, hash_on);    // P10.1
-	    PORT_BIT_SETCLR(P6,  0x02, anaout_on);  // P6.1
-	    PORT_BIT_SETCLR(P10, 0x80, check_on);   // P10.7
-	    break;
-
-	case 19: /* P10.2, P6.0, P10.6 */
-	    PORT_BIT_SETCLR(P10, 0x04, hash_on);    // P10.2
-	    PORT_BIT_SETCLR(P6,  0x01, anaout_on);  // P6.0
-	    PORT_BIT_SETCLR(P10, 0x40, check_on);   // P10.6
-	    break;
-
-	case 20: /* P10.3, P5.2, P10.5 */
-	    PORT_BIT_SETCLR(P10, 0x08, hash_on);    // P10.3
-	    PORT_BIT_SETCLR(P5,  0x04, anaout_on);  // P5.2
-	    PORT_BIT_SETCLR(P10, 0x20, check_on);   // P10.5
->>>>>>> 4ee2e168dfece858fa5192b727334dcae342c7db
 	    break;
 
 
@@ -205,11 +141,8 @@ void Cal_Init(void)
 {
     uint8_t i;
 
-<<<<<<< HEAD
     // P4.7 = 0, P15.7 = 1 ( ?    ?     !)
-=======
-    // P4.7 = 0, P15.7 = 1 (??? ??? ????!)
->>>>>>> 4ee2e168dfece858fa5192b727334dcae342c7db
+
     PORT_BIT_SETCLR(P4,  0x80, 0);
     PORT_BIT_SETCLR(P15, 0x80, 1);
 
@@ -222,11 +155,8 @@ void Eol_Init(void)
 {
     uint8_t i;
 
-<<<<<<< HEAD
     // P4.7 = 1, P15.7 = 0 ( ?    ?     !)
-=======
-    // P4.7 = 1, P15.7 = 0 (??? ??? ????!)
->>>>>>> 4ee2e168dfece858fa5192b727334dcae342c7db
+
     PORT_BIT_SETCLR(P4,  0x80, 1);
     PORT_BIT_SETCLR(P15, 0x80, 1);