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@ -72,65 +72,66 @@ void Gate_SetByNum(uint8_t ch, uint8_t hash_on, uint8_t anaout_on, uint8_t check |
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PORT_BIT_SETCLR(P10, 0x10, check_on); // P10.4
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PORT_BIT_SETCLR(P10, 0x10, check_on); // P10.4
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break; |
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break; |
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case 11: /* P10.3, P5.2, P10.5 */ |
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case 11: /* P9.2, P13.0, P1.4 */ |
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PORT_BIT_SETCLR(P10, 0x08, hash_on); // P10.3
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PORT_BIT_SETCLR(P9, 0x04, hash_on); // P9.2
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PORT_BIT_SETCLR(P5, 0x04, anaout_on); // P5.2
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PORT_BIT_SETCLR(P13, 0x01, anaout_on); // P13.0
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PORT_BIT_SETCLR(P10, 0x20, check_on); // P10.5
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PORT_BIT_SETCLR(P1, 0x10, check_on); // P1.4
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break; |
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break; |
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case 12: /* P10.2, P6.0, P10.6 */ |
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case 12: /* P9.3, P7.7, P1.3 */ |
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PORT_BIT_SETCLR(P10, 0x04, hash_on); // P10.2
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PORT_BIT_SETCLR(P9, 0x08, hash_on); // P9.3
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PORT_BIT_SETCLR(P6, 0x01, anaout_on); // P6.0
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PORT_BIT_SETCLR(P7, 0x80, anaout_on); // P7.7
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PORT_BIT_SETCLR(P10, 0x40, check_on); // P10.6
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PORT_BIT_SETCLR(P1, 0x08, check_on); // P1.3
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break; |
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break; |
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case 13: /* P10.1, P6.1, P10.7 */ |
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case 13: /* P9.4, P7.6, P1.0 */ |
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PORT_BIT_SETCLR(P10, 0x02, hash_on); // P10.1
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PORT_BIT_SETCLR(P9, 0x10, hash_on); // P9.4
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PORT_BIT_SETCLR(P6, 0x02, anaout_on); // P6.1
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PORT_BIT_SETCLR(P7, 0x40, anaout_on); // P7.6
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PORT_BIT_SETCLR(P10, 0x80, check_on); // P10.7
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PORT_BIT_SETCLR(P1, 0x01, check_on); // P1.0
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break; |
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break; |
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case 14: /* P10.0, P7.2, P5.7 */ |
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case 14: /* P9.5, P7.4, P5.4 */ |
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PORT_BIT_SETCLR(P10, 0x01, hash_on); // P10.0
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PORT_BIT_SETCLR(P9, 0x20, hash_on); // P9.5
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PORT_BIT_SETCLR(P7, 0x04, anaout_on); // P7.2
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PORT_BIT_SETCLR(P7, 0x10, anaout_on); // P7.4
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PORT_BIT_SETCLR(P5, 0x80, check_on); // P5.7
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PORT_BIT_SETCLR(P5, 0x10, check_on); // P5.4
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break; |
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case 15: /* P9.6, P7.5, P5.5 */ |
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PORT_BIT_SETCLR(P9, 0x40, hash_on); // P9.6
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PORT_BIT_SETCLR(P7, 0x20, anaout_on); // P7.5
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PORT_BIT_SETCLR(P5, 0x20, check_on); // P5.5
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break; |
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break; |
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case 15: /* P9.7, P7.3, P5.6 */ |
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case 16: /* P9.7, P7.3, P5.6 */ |
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PORT_BIT_SETCLR(P9, 0x80, hash_on); // P9.7
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PORT_BIT_SETCLR(P9, 0x80, hash_on); // P9.7
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PORT_BIT_SETCLR(P7, 0x08, anaout_on); // P7.3
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PORT_BIT_SETCLR(P7, 0x08, anaout_on); // P7.3
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PORT_BIT_SETCLR(P5, 0x40, check_on); // P5.6
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PORT_BIT_SETCLR(P5, 0x40, check_on); // P5.6
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break; |
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break; |
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case 16: /* P9.6, P7.5, P5.5 */ |
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case 17: /* P10.0, P7.2, P5.7 */ |
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PORT_BIT_SETCLR(P9, 0x40, hash_on); // P9.6
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PORT_BIT_SETCLR(P10, 0x01, hash_on); // P10.0
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PORT_BIT_SETCLR(P7, 0x20, anaout_on); // P7.5
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PORT_BIT_SETCLR(P7, 0x04, anaout_on); // P7.2
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PORT_BIT_SETCLR(P5, 0x20, check_on); // P5.5
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PORT_BIT_SETCLR(P5, 0x80, check_on); // P5.7
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break; |
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break; |
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case 17: /* P9.5, P7.4, P5.4 */ |
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case 18: /* P10.1, P6.1, P10.7 */ |
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PORT_BIT_SETCLR(P9, 0x20, hash_on); // P9.5
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PORT_BIT_SETCLR(P10, 0x02, hash_on); // P10.1
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PORT_BIT_SETCLR(P7, 0x10, anaout_on); // P7.4
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PORT_BIT_SETCLR(P6, 0x02, anaout_on); // P6.1
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PORT_BIT_SETCLR(P5, 0x10, check_on); // P5.4
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PORT_BIT_SETCLR(P10, 0x80, check_on); // P10.7
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break; |
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break; |
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case 18: /* P9.4, P7.6, P1.0 */ |
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case 19: /* P10.2, P6.0, P10.6 */ |
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PORT_BIT_SETCLR(P9, 0x10, hash_on); // P9.4
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PORT_BIT_SETCLR(P10, 0x04, hash_on); // P10.2
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PORT_BIT_SETCLR(P7, 0x40, anaout_on); // P7.6
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PORT_BIT_SETCLR(P6, 0x01, anaout_on); // P6.0
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PORT_BIT_SETCLR(P1, 0x01, check_on); // P1.0
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PORT_BIT_SETCLR(P10, 0x40, check_on); // P10.6
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break; |
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break; |
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case 19: /* P9.3, P7.7, P1.3 */ |
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case 20: /* P10.3, P5.2, P10.5 */ |
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PORT_BIT_SETCLR(P9, 0x08, hash_on); // P9.3
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PORT_BIT_SETCLR(P10, 0x08, hash_on); // P10.3
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PORT_BIT_SETCLR(P7, 0x80, anaout_on); // P7.7
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PORT_BIT_SETCLR(P5, 0x04, anaout_on); // P5.2
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PORT_BIT_SETCLR(P1, 0x08, check_on); // P1.3
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PORT_BIT_SETCLR(P10, 0x20, check_on); // P10.5
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break; |
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break; |
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case 20: /* P9.2, P13.0, P1.4 */ |
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PORT_BIT_SETCLR(P9, 0x04, hash_on); // P9.2
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PORT_BIT_SETCLR(P13, 0x01, anaout_on); // P13.0
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PORT_BIT_SETCLR(P1, 0x10, check_on); // P1.4
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break; |
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default: |
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default: |
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break; |
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break; |
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